From 61ca83e099ce9b08b0dcbfaac65a2e2870d58413 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 16 Apr 2019 13:24:54 -0700 Subject: [PATCH] Remove write_verilog call --- backends/aiger/xaiger.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index bd7347a19..99ca4f8d5 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -630,7 +630,7 @@ struct XAigerWriter RTLIL::Selection& sel = holes_module->design->selection_stack.back(); sel.select(holes_module); - Pass::call(holes_module->design, "flatten; aigmap; write_verilog -noexpr -norename holes.v"); + Pass::call(holes_module->design, "flatten; aigmap"); holes_module->design->selection_stack.pop_back(); -- 2.30.2