From 61d0b9f52c6be4a4a64c30ea3a2a93ef8260c67b Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Thu, 26 Jul 2012 11:41:26 -0700 Subject: [PATCH] intel: Make the length for PIPE_CONTROL explicit. PIPE_CONTROL has variable length, depending upon generation and whether we want to do 32-bit or 64-bit data writes. Make it explicit, rather than hiding a length of 4 in the #define for _3DSTATE_PIPE_CONTROL. Generated by s/3DSTATE_PIPE_CONTROL/3DSTATE_PIPE_CONTROL | (4 - 2)/g. This is equivalent since the #define used to have | 2 in it. A grep through the sources shows that all instances have been converted, so it's safe to remove the | 2 from the #define. Signed-off-by: Daniel Vetter Signed-off-by: Kenneth Graunke Reviewed-by: Daniel Vetter Reviewed-by: Eric Anholt --- src/mesa/drivers/dri/i965/brw_queryobj.c | 20 +++++++++---------- src/mesa/drivers/dri/i965/gen6_vs_state.c | 2 +- .../drivers/dri/intel/intel_batchbuffer.c | 16 +++++++-------- src/mesa/drivers/dri/intel/intel_reg.h | 2 +- 4 files changed, 20 insertions(+), 20 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_queryobj.c b/src/mesa/drivers/dri/i965/brw_queryobj.c index 240fe32bdc5..921fecd9e43 100644 --- a/src/mesa/drivers/dri/i965/brw_queryobj.c +++ b/src/mesa/drivers/dri/i965/brw_queryobj.c @@ -132,7 +132,7 @@ brw_begin_query(struct gl_context *ctx, struct gl_query_object *q) if (intel->gen >= 6) { BEGIN_BATCH(4); - OUT_BATCH(_3DSTATE_PIPE_CONTROL); + OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); OUT_BATCH(PIPE_CONTROL_WRITE_TIMESTAMP); OUT_RELOC(query->bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, @@ -143,7 +143,7 @@ brw_begin_query(struct gl_context *ctx, struct gl_query_object *q) } else { BEGIN_BATCH(4); - OUT_BATCH(_3DSTATE_PIPE_CONTROL | + OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2) | PIPE_CONTROL_WRITE_TIMESTAMP); OUT_RELOC(query->bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, @@ -202,7 +202,7 @@ brw_end_query(struct gl_context *ctx, struct gl_query_object *q) case GL_TIME_ELAPSED_EXT: if (intel->gen >= 6) { BEGIN_BATCH(4); - OUT_BATCH(_3DSTATE_PIPE_CONTROL); + OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); OUT_BATCH(PIPE_CONTROL_WRITE_TIMESTAMP); OUT_RELOC(query->bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, @@ -213,7 +213,7 @@ brw_end_query(struct gl_context *ctx, struct gl_query_object *q) } else { BEGIN_BATCH(4); - OUT_BATCH(_3DSTATE_PIPE_CONTROL | + OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2) | PIPE_CONTROL_WRITE_TIMESTAMP); OUT_RELOC(query->bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, @@ -340,12 +340,12 @@ brw_emit_query_begin(struct brw_context *brw) BEGIN_BATCH(8); /* workaround: CS stall required before depth stall. */ - OUT_BATCH(_3DSTATE_PIPE_CONTROL); + OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); OUT_BATCH(PIPE_CONTROL_CS_STALL); OUT_BATCH(0); /* write address */ OUT_BATCH(0); /* write data */ - OUT_BATCH(_3DSTATE_PIPE_CONTROL); + OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); OUT_BATCH(PIPE_CONTROL_DEPTH_STALL | PIPE_CONTROL_WRITE_DEPTH_COUNT); OUT_RELOC(brw->query.bo, @@ -357,7 +357,7 @@ brw_emit_query_begin(struct brw_context *brw) } else { BEGIN_BATCH(4); - OUT_BATCH(_3DSTATE_PIPE_CONTROL | + OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2) | PIPE_CONTROL_DEPTH_STALL | PIPE_CONTROL_WRITE_DEPTH_COUNT); /* This object could be mapped cacheable, but we don't have an exposed @@ -397,12 +397,12 @@ brw_emit_query_end(struct brw_context *brw) if (intel->gen >= 6) { BEGIN_BATCH(8); /* workaround: CS stall required before depth stall. */ - OUT_BATCH(_3DSTATE_PIPE_CONTROL); + OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); OUT_BATCH(PIPE_CONTROL_CS_STALL); OUT_BATCH(0); /* write address */ OUT_BATCH(0); /* write data */ - OUT_BATCH(_3DSTATE_PIPE_CONTROL); + OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); OUT_BATCH(PIPE_CONTROL_DEPTH_STALL | PIPE_CONTROL_WRITE_DEPTH_COUNT); OUT_RELOC(brw->query.bo, @@ -414,7 +414,7 @@ brw_emit_query_end(struct brw_context *brw) } else { BEGIN_BATCH(4); - OUT_BATCH(_3DSTATE_PIPE_CONTROL | + OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2) | PIPE_CONTROL_DEPTH_STALL | PIPE_CONTROL_WRITE_DEPTH_COUNT); OUT_RELOC(brw->query.bo, diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c b/src/mesa/drivers/dri/i965/gen6_vs_state.c index 3392a9f442e..c562cc788ef 100644 --- a/src/mesa/drivers/dri/i965/gen6_vs_state.c +++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c @@ -216,7 +216,7 @@ upload_vs_state(struct brw_context *brw) intel_emit_post_sync_nonzero_flush(intel); BEGIN_BATCH(4); - OUT_BATCH(_3DSTATE_PIPE_CONTROL); + OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); OUT_BATCH(PIPE_CONTROL_DEPTH_STALL | PIPE_CONTROL_INSTRUCTION_FLUSH | PIPE_CONTROL_STATE_CACHE_INVALIDATE); diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c index a1b5ccc4204..ac133ee8e03 100644 --- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c @@ -380,21 +380,21 @@ intel_emit_depth_stall_flushes(struct intel_context *intel) assert(intel->gen >= 6 && intel->gen <= 7); BEGIN_BATCH(4); - OUT_BATCH(_3DSTATE_PIPE_CONTROL); + OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); OUT_BATCH(PIPE_CONTROL_DEPTH_STALL); OUT_BATCH(0); /* address */ OUT_BATCH(0); /* write data */ ADVANCE_BATCH() BEGIN_BATCH(4); - OUT_BATCH(_3DSTATE_PIPE_CONTROL); + OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); OUT_BATCH(PIPE_CONTROL_DEPTH_CACHE_FLUSH); OUT_BATCH(0); /* address */ OUT_BATCH(0); /* write data */ ADVANCE_BATCH(); BEGIN_BATCH(4); - OUT_BATCH(_3DSTATE_PIPE_CONTROL); + OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); OUT_BATCH(PIPE_CONTROL_DEPTH_STALL); OUT_BATCH(0); /* address */ OUT_BATCH(0); /* write data */ @@ -415,7 +415,7 @@ gen7_emit_vs_workaround_flush(struct intel_context *intel) assert(intel->gen == 7); BEGIN_BATCH(4); - OUT_BATCH(_3DSTATE_PIPE_CONTROL); + OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); OUT_BATCH(PIPE_CONTROL_DEPTH_STALL | PIPE_CONTROL_WRITE_IMMEDIATE); OUT_RELOC(intel->batch.workaround_bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); @@ -467,7 +467,7 @@ intel_emit_post_sync_nonzero_flush(struct intel_context *intel) return; BEGIN_BATCH(4); - OUT_BATCH(_3DSTATE_PIPE_CONTROL); + OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); OUT_BATCH(PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD); OUT_BATCH(0); /* address */ @@ -475,7 +475,7 @@ intel_emit_post_sync_nonzero_flush(struct intel_context *intel) ADVANCE_BATCH(); BEGIN_BATCH(4); - OUT_BATCH(_3DSTATE_PIPE_CONTROL); + OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE); OUT_RELOC(intel->batch.workaround_bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); @@ -514,7 +514,7 @@ intel_batchbuffer_emit_mi_flush(struct intel_context *intel) } BEGIN_BATCH(4); - OUT_BATCH(_3DSTATE_PIPE_CONTROL); + OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); OUT_BATCH(PIPE_CONTROL_INSTRUCTION_FLUSH | PIPE_CONTROL_WRITE_FLUSH | PIPE_CONTROL_DEPTH_CACHE_FLUSH | @@ -528,7 +528,7 @@ intel_batchbuffer_emit_mi_flush(struct intel_context *intel) } } else if (intel->gen >= 4) { BEGIN_BATCH(4); - OUT_BATCH(_3DSTATE_PIPE_CONTROL | + OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2) | PIPE_CONTROL_WRITE_FLUSH | PIPE_CONTROL_NO_WRITE); OUT_BATCH(0); /* write address */ diff --git a/src/mesa/drivers/dri/intel/intel_reg.h b/src/mesa/drivers/dri/intel/intel_reg.h index e2a6ee20311..2c75a8e35d5 100644 --- a/src/mesa/drivers/dri/intel/intel_reg.h +++ b/src/mesa/drivers/dri/intel/intel_reg.h @@ -58,7 +58,7 @@ * PIPE_CONTROL operation, a combination MI_FLUSH and register write with * additional flushing control. */ -#define _3DSTATE_PIPE_CONTROL (CMD_3D | (3 << 27) | (2 << 24) | 2) +#define _3DSTATE_PIPE_CONTROL (CMD_3D | (3 << 27) | (2 << 24)) #define PIPE_CONTROL_CS_STALL (1 << 20) #define PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET (1 << 19) #define PIPE_CONTROL_TLB_INVALIDATE (1 << 18) -- 2.30.2