From 61d77884191f2094ac67f06ba9d8fce472a7708b Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 6 May 2022 22:48:16 +0100 Subject: [PATCH] --- openpower/sv/SimpleV_rationale.mdwn | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index 554966aac..848c2e8c4 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -738,5 +738,16 @@ well-defined workloads, expressed as a perfecly normal sequential program, compiled to a standard well-known ISA, to have the potential of being offloaded transparently to Parallel Compute Engines, all without the Software Developer being excessively burdened with -a Programming Paradigm that is alien to both their experience and training, -as well as common knowledge. +a Parallel-Processing Paradigm that is alien to both their experience +and training, as well as common knowledge. + +Will it be that easy? ZOLC is, honestly, in its current incarnation, +not that straightforward: programs +have to be "massaged" by tools that insert intrinsics into the +source code, in order to identify the Basic Blocks that the Zero-Overhead +Loops can run. Can this be merged into standard gcc and llvm +compilers? As intrinsics: of course. Can it become part of auto-vectorisation? Probably, +if an infinite supply of money and engineering time is thrown at it. +Is a half-way-house solution of compiler intrinsics good enough? +Intel, ARM, MIPS, Power ISA and RISC-V have all already said "yes" on that, +for several decades, and advanced programmers are comfortable with it. -- 2.30.2