From 61eef7157e7a203eadd2617adf4f655bf239d998 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 3 Oct 2018 07:16:34 +0100 Subject: [PATCH] decided not to change the behaviour of LOAD/STORE --- riscv/insn_template_sv.cc | 6 +----- riscv/sv.cc | 8 -------- riscv/sv_decode.h | 8 ++------ 3 files changed, 3 insertions(+), 19 deletions(-) diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc index 4a547a6..7a1884c 100644 --- a/riscv/insn_template_sv.cc +++ b/riscv/insn_template_sv.cc @@ -20,12 +20,8 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc) unsigned int floatintmap = REGS_PATTERN; reg_t dest_pred = ~0x0; bool ldimm_sv = false; -#ifdef INSN_TYPE_LOAD - bool ldimm_sv = true; -#endif sv_insn_t insn(p, bits, floatintmap, - dest_pred, dest_pred, dest_pred, dest_pred, - ldimm_sv); + dest_pred, dest_pred, dest_pred, dest_pred); bool zeroing; #if defined(USING_REG_RD) || defined(USING_REG_FRD) // use the ORIGINAL, i.e. NON-REDIRECTED, register here diff --git a/riscv/sv.cc b/riscv/sv.cc index bb791b8..90ef354 100644 --- a/riscv/sv.cc +++ b/riscv/sv.cc @@ -165,11 +165,3 @@ uint64_t sv_insn_t::predicated(uint64_t reg, int offs, uint64_t pred) return 0; } -uint64_t sv_insn_t::i_imm() -{ - if (ldst_imm_mode == false) - { - return insn_t::i_imm(); - } - return insn_t::i_imm(); // TODO -} diff --git a/riscv/sv_decode.h b/riscv/sv_decode.h index cf23ffd..5d2b2fc 100644 --- a/riscv/sv_decode.h +++ b/riscv/sv_decode.h @@ -21,8 +21,7 @@ class sv_insn_t: public insn_t { public: sv_insn_t(processor_t *pr, insn_bits_t bits, unsigned int f, - uint64_t &p_rd, uint64_t &p_rs1, uint64_t &p_rs2, uint64_t &p_rs3, - bool ldimm_mode) : + uint64_t &p_rd, uint64_t &p_rs1, uint64_t &p_rs2, uint64_t &p_rs3) : insn_t(bits), p(pr), vloop_continue(false), fimap(f), cached_rd(0xff), cached_rs1(0xff), cached_rs2(0xff), cached_rs3(0xff), @@ -30,8 +29,7 @@ public: offs_rs2(0), offs_rs3(0), new_offs_rd(0), new_offs_rs1(0), new_offs_rs2(0), new_offs_rs3(0), - prd(p_rd), prs1(p_rs1), prs2(p_rs2), prs3(p_rs3), - ldst_imm_mode(ldimm_mode) {} + prd(p_rd), prs1(p_rs1), prs2(p_rs2), prs3(p_rs3) {} uint64_t rd () { return predicated(_rd (), offs_rd , prd); } uint64_t rs1() { return predicated(_rs1(), offs_rs1, prs1); } uint64_t rs2() { return predicated(_rs2(), offs_rs2, prs2); } @@ -40,7 +38,6 @@ public: uint64_t rvc_rs1s() { return predicated(_rvc_rs1s(), offs_rs1, prs1); } uint64_t rvc_rs2 () { return predicated(_rvc_rs2 (), offs_rs2, prs2); } uint64_t rvc_rs2s() { return predicated(_rvc_rs2s(), offs_rs2, prs2); } - uint64_t i_imm(); uint64_t _rd () { return _remap(insn_t::rd (), fimap & REG_RD , offs_rd , cached_rd, new_offs_rd); } @@ -99,7 +96,6 @@ private: uint64_t &prs1; uint64_t &prs2; uint64_t &prs3; - bool ldst_imm_mode; // remaps the register through the lookup table. // will need to take the current loop index/offset somehow -- 2.30.2