From 61f0ccffa36f96fc1a1f20fd8d4ec2bfb911140d Mon Sep 17 00:00:00 2001 From: Richard Earnshaw Date: Sat, 15 May 2004 12:41:35 +0000 Subject: [PATCH] arm.h (TARGET_APCS_32): Delete. * arm.h (TARGET_APCS_32): Delete. (TARGET_MMU_TRAPS): Delete. (TARGET_CPU_CPP_BUILTINS): Unconditionally define __APCS_32__. Never define __APCS_26__. (CPP_SPEC): Remove checking of -mapcs-{26,32}. (ARM_FLAG_APCS_32, ARM_FLAG_MMU_TRAPS): Delete. (TARGET_SWITCHES): Remove alignment_traps and apcs-{26,32} switches. (prog_mode_type): Delete. (PROMOTE_MODE): Always promote unsigned for HImode. (SECONDARY_INPUT_RELOAD_CLASS): Simplify. (MASK_RETURN_ADDR): Simplify. * arm.c (arm_prgmode): Delete. (arm_override_options, arm_gen_rotated_half_load): Simplify. (print_multi_reg, output_return_instruction): Simplify. (arm_output_epilogue, arm_final_prescan_insn): Simplify. (arm_return_addr): Simplify. * arm.md (prog_mode): Delete. (conds): Simplify. (zero_extendhisi2, extendhisi2, movhi, movhi_bytes): Simplify. (rotated_loadsi, movhi_insn_littleend, movhi_insn_bigend): Delete. (loadhi_si_bigend, loadhi_preinc, loadhi_shiftpreinc): Delete. (loadhi_shiftpredec): Delete. (peephole for post-increment on HImode load): Delete. * arm/crtn.asm: (FUNC_END): Simplify. * arm/lib1funcs.asm: Remove APCS-26 return macros. * arm/aof.h, arm/coff.h arm/elf.h arm/linux-elf.h arm/netbsd-elf.h * arm/netbsd.h arm/pe.h arm/semi.h arm/semiaof.h arm/unknown-elf.h * arm/vxworks.h arm/wince-pe.h: Tidy TARGET_DEFAULTS and MULTILIB_DEFAULTS as required. * arm/t-arm-elf arm/t-linux arm/t-pe arm/t-semi arm/t-wince-pe * arm/t-xscale-coff arm/t-xscale-elf arm/uclinux-elf: Tidy MULTILIB variables as required. * doc/invoke.texi (ARM Options): Remove obsolete flags. From-SVN: r81881 --- gcc/ChangeLog | 36 +++++ gcc/config/arm/aof.h | 3 +- gcc/config/arm/arm.c | 136 ++++------------ gcc/config/arm/arm.h | 53 +----- gcc/config/arm/arm.md | 301 ++++------------------------------- gcc/config/arm/coff.h | 6 +- gcc/config/arm/crtn.asm | 6 +- gcc/config/arm/elf.h | 4 +- gcc/config/arm/lib1funcs.asm | 17 +- gcc/config/arm/linux-elf.h | 7 +- gcc/config/arm/netbsd-elf.h | 4 +- gcc/config/arm/netbsd.h | 9 +- gcc/config/arm/pe.h | 11 +- gcc/config/arm/semi.h | 5 +- gcc/config/arm/semiaof.h | 10 +- gcc/config/arm/t-arm-elf | 7 +- gcc/config/arm/t-linux | 5 - gcc/config/arm/t-pe | 4 +- gcc/config/arm/t-semi | 6 +- gcc/config/arm/t-wince-pe | 6 +- gcc/config/arm/t-xscale-coff | 1 - gcc/config/arm/t-xscale-elf | 1 - gcc/config/arm/uclinux-elf.h | 4 +- gcc/config/arm/unknown-elf.h | 8 +- gcc/config/arm/vxworks.h | 14 +- gcc/config/arm/wince-pe.h | 8 +- gcc/doc/invoke.texi | 48 ------ 27 files changed, 153 insertions(+), 567 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 65f431ad9a7..dfd84927c00 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,39 @@ +2004-05-15 Richard Earnshaw + + * arm.h (TARGET_APCS_32): Delete. + (TARGET_MMU_TRAPS): Delete. + (TARGET_CPU_CPP_BUILTINS): Unconditionally define __APCS_32__. Never + define __APCS_26__. + (CPP_SPEC): Remove checking of -mapcs-{26,32}. + (ARM_FLAG_APCS_32, ARM_FLAG_MMU_TRAPS): Delete. + (TARGET_SWITCHES): Remove alignment_traps and apcs-{26,32} switches. + (prog_mode_type): Delete. + (PROMOTE_MODE): Always promote unsigned for HImode. + (SECONDARY_INPUT_RELOAD_CLASS): Simplify. + (MASK_RETURN_ADDR): Simplify. + * arm.c (arm_prgmode): Delete. + (arm_override_options, arm_gen_rotated_half_load): Simplify. + (print_multi_reg, output_return_instruction): Simplify. + (arm_output_epilogue, arm_final_prescan_insn): Simplify. + (arm_return_addr): Simplify. + * arm.md (prog_mode): Delete. + (conds): Simplify. + (zero_extendhisi2, extendhisi2, movhi, movhi_bytes): Simplify. + (rotated_loadsi, movhi_insn_littleend, movhi_insn_bigend): Delete. + (loadhi_si_bigend, loadhi_preinc, loadhi_shiftpreinc): Delete. + (loadhi_shiftpredec): Delete. + (peephole for post-increment on HImode load): Delete. + * arm/crtn.asm: (FUNC_END): Simplify. + * arm/lib1funcs.asm: Remove APCS-26 return macros. + * arm/aof.h, arm/coff.h arm/elf.h arm/linux-elf.h arm/netbsd-elf.h + * arm/netbsd.h arm/pe.h arm/semi.h arm/semiaof.h arm/unknown-elf.h + * arm/vxworks.h arm/wince-pe.h: Tidy TARGET_DEFAULTS and + MULTILIB_DEFAULTS as required. + * arm/t-arm-elf arm/t-linux arm/t-pe arm/t-semi arm/t-wince-pe + * arm/t-xscale-coff arm/t-xscale-elf arm/uclinux-elf: Tidy MULTILIB + variables as required. + * doc/invoke.texi (ARM Options): Remove obsolete flags. + 2004-05-15 Alan Modra * config/rs6000/rs6000.c (rs6000_va_arg ): Don't use diff --git a/gcc/config/arm/aof.h b/gcc/config/arm/aof.h index 56057fca90a..aae95d41e8c 100644 --- a/gcc/config/arm/aof.h +++ b/gcc/config/arm/aof.h @@ -35,8 +35,7 @@ #define ENDFILE_SPEC "crtend.o%s" #ifndef ASM_SPEC -#define ASM_SPEC "%{g -g} -arch 4 \ --apcs 3%{mapcs-32:/32bit}%{mapcs-26:/26bit}%{!mapcs-26:%{!macps-32:/26bit}}" +#define ASM_SPEC "%{g -g} -arch 4 -apcs 3/32bit" #endif #ifndef LIB_SPEC diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index acbdb77f15b..6e85b11de89 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -301,9 +301,6 @@ enum float_abi_type arm_float_abi; /* Which ABI to use. */ enum arm_abi_type arm_abi; -/* What program mode is the cpu running in? 26-bit mode or 32-bit mode. */ -enum prog_mode_type arm_prgmode; - /* Set by the -mfpu=... option. */ const char * target_fpu_name = NULL; @@ -672,17 +669,12 @@ arm_override_options (void) { sought |= (FL_THUMB | FL_MODE32); - /* Force apcs-32 to be used for interworking. */ - target_flags |= ARM_FLAG_APCS_32; - /* There are no ARM processors that support both APCS-26 and interworking. Therefore we force FL_MODE26 to be removed from insn_flags here (if it was set), so that the search below will always be able to find a compatible processor. */ insn_flags &= ~FL_MODE26; } - else if (!TARGET_APCS_32) - sought |= FL_MODE26; if (sought != 0 && ((sought & insn_flags) != sought)) { @@ -705,12 +697,10 @@ arm_override_options (void) ought to use the -mcpu= command line option to override the default CPU type. - Unfortunately this does not work with multilibing. We - need to be able to support multilibs for -mapcs-26 and for - -mthumb-interwork and there is no CPU that can support both - options. Instead if we cannot find a cpu that has both the - characteristics of the default cpu and the given command line - options we scan the array again looking for a best match. */ + If we cannot find a cpu that has both the + characteristics of the default cpu and the given + command line options we scan the array again looking + for a best match. */ for (sel = all_cores; sel->name != NULL; sel++) if ((sel->flags & sought) == sought) { @@ -748,21 +738,6 @@ arm_override_options (void) /* Make sure that the processor choice does not conflict with any of the other command line choices. */ - if (TARGET_APCS_32 && !(insn_flags & FL_MODE32)) - { - /* If APCS-32 was not the default then it must have been set by the - user, so issue a warning message. If the user has specified - "-mapcs-32 -mcpu=arm2" then we loose here. */ - if ((TARGET_DEFAULT & ARM_FLAG_APCS_32) == 0) - warning ("target CPU does not support APCS-32" ); - target_flags &= ~ARM_FLAG_APCS_32; - } - else if (!TARGET_APCS_32 && !(insn_flags & FL_MODE26)) - { - warning ("target CPU does not support APCS-26" ); - target_flags |= ARM_FLAG_APCS_32; - } - if (TARGET_INTERWORK && !(insn_flags & FL_THUMB)) { warning ("target CPU does not support interworking" ); @@ -793,14 +768,6 @@ arm_override_options (void) if (TARGET_ARM && TARGET_CALLER_INTERWORKING) warning ("enabling caller interworking support is only meaningful when compiling for the Thumb"); - /* If interworking is enabled then APCS-32 must be selected as well. */ - if (TARGET_INTERWORK) - { - if (!TARGET_APCS_32) - warning ("interworking forces APCS-32 to be used" ); - target_flags |= ARM_FLAG_APCS_32; - } - if (TARGET_APCS_STACK && !TARGET_APCS_FRAME) { warning ("-mapcs-stack-check incompatible with -mno-apcs-frame"); @@ -963,8 +930,6 @@ arm_override_options (void) && (tune_flags & FL_MODE32) == 0) flag_schedule_insns = flag_schedule_insns_after_reload = 0; - arm_prgmode = TARGET_APCS_32 ? PROG_MODE_PROG32 : PROG_MODE_PROG26; - /* Override the default structure alignment for AAPCS ABI. */ if (arm_abi == ARM_ABI_AAPCS) arm_structure_size_boundary = 8; @@ -6136,8 +6101,7 @@ arm_gen_rotated_half_load (rtx memref) } /* If we aren't allowed to generate unaligned addresses, then fail. */ - if (TARGET_MMU_TRAPS - && ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0))) + if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0)) return NULL; base = gen_rtx_MEM (SImode, plus_constant (base, offset & ~2)); @@ -7892,20 +7856,7 @@ print_multi_reg (FILE *stream, const char *instr, int reg, int mask) not_first = TRUE; } - fprintf (stream, "}"); - - /* Add a ^ character for the 26-bit ABI, but only if we were loading - the PC. Otherwise we would generate an UNPREDICTABLE instruction. - Strictly speaking the instruction would be unpredictable only if - we were writing back the base register as well, but since we never - want to generate an LDM type 2 instruction (register bank switching) - which is what you get if the PC is not being loaded, we do not need - to check for writeback. */ - if (! TARGET_APCS_32 - && ((mask & (1 << PC_REGNUM)) != 0)) - fprintf (stream, "^"); - - fprintf (stream, "\n"); + fprintf (stream, "}\n"); } @@ -9210,7 +9161,7 @@ output_return_instruction (rtx operand, int really_return, int reverse) if (reg <= LAST_ARM_REGNUM && (reg != LR_REGNUM || ! really_return - || (TARGET_APCS_32 && ! IS_INTERRUPT (func_type)))) + || ! IS_INTERRUPT (func_type))) { sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional, (reg == LR_REGNUM) ? return_reg : reg_names[reg]); @@ -9270,20 +9221,8 @@ output_return_instruction (rtx operand, int really_return, int reverse) if (live_regs_mask & (1 << LR_REGNUM)) { sprintf (p, "%s%%|%s}", first ? "" : ", ", return_reg); - /* Decide if we need to add the ^ symbol to the end of the - register list. This causes the saved condition codes - register to be copied into the current condition codes - register. We do the copy if we are conforming to the 32-bit - ABI and this is an interrupt function, or if we are - conforming to the 26-bit ABI. There is a special case for - the 26-bit ABI however, which is if we are writing back the - stack pointer but not loading the PC. In this case adding - the ^ symbol would create a type 2 LDM instruction, where - writeback is UNPREDICTABLE. We are safe in leaving the ^ - character off in this case however, since the actual return - instruction will be a MOVS which will restore the CPSR. */ - if ((TARGET_APCS_32 && IS_INTERRUPT (func_type)) - || (! TARGET_APCS_32 && really_return)) + /* If returning from an interrupt, restore the CPSR. */ + if (IS_INTERRUPT (func_type)) strcat (p, "^"); } else @@ -9323,12 +9262,11 @@ output_return_instruction (rtx operand, int really_return, int reverse) default: /* ARMv5 implementations always provide BX, so interworking - is the default unless APCS-26 is in use. */ - if ((insn_flags & FL_ARCH5) != 0 && TARGET_APCS_32) + is the default. */ + if ((insn_flags & FL_ARCH5) != 0) sprintf (instr, "bx%s\t%%|lr", conditional); else - sprintf (instr, "mov%s%s\t%%|pc, %%|lr", - conditional, TARGET_APCS_32 ? "" : "s"); + sprintf (instr, "mov%s\t%%|pc, %%|lr", conditional); break; } @@ -9806,10 +9744,8 @@ arm_output_epilogue (rtx sibling) /* Similarly we may have been able to load LR into the PC even if we did not create a stack frame. */ ; - else if (TARGET_APCS_32) - asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM); else - asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM); + asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM); break; } @@ -11303,32 +11239,27 @@ arm_final_prescan_insn (rtx insn) break; case CALL_INSN: - /* If using 32-bit addresses the cc is not preserved over - calls. */ - if (TARGET_APCS_32) - { - /* Succeed if the following insn is the target label, - or if the following two insns are a barrier and - the target label. */ - this_insn = next_nonnote_insn (this_insn); - if (this_insn && GET_CODE (this_insn) == BARRIER) - this_insn = next_nonnote_insn (this_insn); + /* Succeed if the following insn is the target label, or + if the following two insns are a barrier and the + target label. */ + this_insn = next_nonnote_insn (this_insn); + if (this_insn && GET_CODE (this_insn) == BARRIER) + this_insn = next_nonnote_insn (this_insn); - if (this_insn && this_insn == label - && insns_skipped < max_insns_skipped) + if (this_insn && this_insn == label + && insns_skipped < max_insns_skipped) + { + if (jump_clobbers) { - if (jump_clobbers) - { - arm_ccfsm_state = 2; - this_insn = next_nonnote_insn (this_insn); - } - else - arm_ccfsm_state = 1; - succeed = TRUE; + arm_ccfsm_state = 2; + this_insn = next_nonnote_insn (this_insn); } else - fail = TRUE; + arm_ccfsm_state = 1; + succeed = TRUE; } + else + fail = TRUE; break; case JUMP_INSN: @@ -13173,14 +13104,7 @@ arm_return_addr (int count, rtx frame ATTRIBUTE_UNUSED) if (count != 0) return NULL_RTX; - if (TARGET_APCS_32) - return get_hard_reg_initial_val (Pmode, LR_REGNUM); - else - { - rtx lr = gen_rtx_AND (Pmode, gen_rtx_REG (Pmode, LR_REGNUM), - GEN_INT (RETURN_ADDR_MASK26)); - return get_func_hard_reg_initial_val (cfun, lr); - } + return get_hard_reg_initial_val (Pmode, LR_REGNUM); } /* Do anything needed before RTL is emitted for each function. */ diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index fe693a83ce1..8241b2cb95e 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -36,6 +36,7 @@ extern char arm_arch_name[]; /* Define __arm__ even when in thumb mode, for \ consistency with armcc. */ \ builtin_define ("__arm__"); \ + builtin_define ("__APCS_32__"); \ if (TARGET_THUMB) \ builtin_define ("__thumb__"); \ \ @@ -54,11 +55,6 @@ extern char arm_arch_name[]; builtin_define ("__THUMBEL__"); \ } \ \ - if (TARGET_APCS_32) \ - builtin_define ("__APCS_32__"); \ - else \ - builtin_define ("__APCS_26__"); \ - \ if (TARGET_SOFT_FLOAT) \ builtin_define ("__SOFTFP__"); \ \ @@ -149,8 +145,6 @@ extern GTY(()) rtx aof_pic_label; #undef CPP_SPEC #define CPP_SPEC "%(subtarget_cpp_spec) \ -%{mapcs-32:%{mapcs-26: \ - %e-mapcs-26 and -mapcs-32 may not be used together}} \ %{msoft-float:%{mhard-float: \ %e-msoft-float and -mhard_float may not be used together}} \ %{mbig-endian:%{mlittle-endian: \ @@ -201,12 +195,7 @@ extern GTY(()) rtx aof_pic_label; case instruction scheduling becomes very uninteresting. */ #define ARM_FLAG_FPE (1 << 2) -/* Nonzero if destined for a processor in 32-bit program mode. Takes out bit - that assume restoration of the condition flags when returning from a - branch and link (ie a function). */ -#define ARM_FLAG_APCS_32 (1 << 3) - -/* FLAGS 0x0008 and 0x0010 are now spare (used to be arm3/6 selection). */ +/* FLAG 0x0008 now spare (used to be apcs-32 selection). */ /* Nonzero if stack checking should be performed on entry to each function which allocates temporary variables on the stack. */ @@ -220,10 +209,7 @@ extern GTY(()) rtx aof_pic_label; This is equivalent to -fpic. */ #define ARM_FLAG_APCS_REENT (1 << 6) -/* Nonzero if the MMU will trap unaligned word accesses, so shorts must - be loaded using either LDRH or LDRB instructions. */ -#define ARM_FLAG_MMU_TRAPS (1 << 7) - + /* FLAG 0x0080 now spare (used to be alignment traps). */ /* Nonzero if all floating point instructions are missing (and there is no emulator either). Generate function calls for all ops in this case. */ #define ARM_FLAG_SOFT_FLOAT (1 << 8) @@ -276,11 +262,9 @@ extern GTY(()) rtx aof_pic_label; #define TARGET_APCS_FRAME (target_flags & ARM_FLAG_APCS_FRAME) #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE) #define TARGET_FPE (target_flags & ARM_FLAG_FPE) -#define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32) #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK) #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT) #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT) -#define TARGET_MMU_TRAPS (target_flags & ARM_FLAG_MMU_TRAPS) #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT) #define TARGET_SOFT_FLOAT_ABI (arm_float_abi != ARM_FLOAT_ABI_HARD) #define TARGET_HARD_FLOAT (arm_float_abi == ARM_FLOAT_ABI_HARD) @@ -325,10 +309,6 @@ extern GTY(()) rtx aof_pic_label; N_("Store function names in object code") }, \ {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \ {"fpe", ARM_FLAG_FPE, "" }, \ - {"apcs-32", ARM_FLAG_APCS_32, \ - N_("Use the 32-bit version of the APCS") }, \ - {"apcs-26", -ARM_FLAG_APCS_32, \ - N_("Use the 26-bit version of the APCS") }, \ {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \ {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \ {"apcs-float", ARM_FLAG_APCS_FLOAT, \ @@ -337,13 +317,6 @@ extern GTY(()) rtx aof_pic_label; {"apcs-reentrant", ARM_FLAG_APCS_REENT, \ N_("Generate re-entrant, PIC code") }, \ {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \ - {"alignment-traps", ARM_FLAG_MMU_TRAPS, \ - N_("The MMU will trap on unaligned accesses") }, \ - {"no-alignment-traps", -ARM_FLAG_MMU_TRAPS, "" }, \ - {"short-load-bytes", ARM_FLAG_MMU_TRAPS, "" }, \ - {"no-short-load-bytes", -ARM_FLAG_MMU_TRAPS, "" }, \ - {"short-load-words", -ARM_FLAG_MMU_TRAPS, "" }, \ - {"no-short-load-words", ARM_FLAG_MMU_TRAPS, "" }, \ {"soft-float", ARM_FLAG_SOFT_FLOAT, \ N_("Use library calls to perform FP operations") }, \ {"hard-float", -ARM_FLAG_SOFT_FLOAT, \ @@ -446,17 +419,6 @@ struct arm_cpu_select string pointer will be set to the value specified by the user. */ extern struct arm_cpu_select arm_select[]; -enum prog_mode_type -{ - prog_mode26, - prog_mode32 -}; - -/* Recast the program mode class to be the prog_mode attribute. */ -#define arm_prog_mode ((enum attr_prog_mode) arm_prgmode) - -extern enum prog_mode_type arm_prgmode; - /* Which floating point model to use. */ enum arm_fp_model { @@ -617,7 +579,7 @@ extern int arm_is_6_or_7; if (MODE == QImode) \ UNSIGNEDP = 1; \ else if (MODE == HImode) \ - UNSIGNEDP = TARGET_MMU_TRAPS != 0; \ + UNSIGNEDP = 1; \ (MODE) = SImode; \ } @@ -1394,7 +1356,7 @@ enum reg_class (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \ && CONSTANT_P (X)) \ ? GENERAL_REGS : \ - (((MODE) == HImode && ! arm_arch4 && TARGET_MMU_TRAPS \ + (((MODE) == HImode && ! arm_arch4 \ && (GET_CODE (X) == MEM \ || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \ && true_regnum (X) == -1))) \ @@ -2621,9 +2583,8 @@ extern int making_const_table; in 26 bit mode, the condition codes must be masked out of the \ return address. This does not apply to ARM6 and later processors \ when running in 32 bit mode. */ \ - ((!TARGET_APCS_32) ? (gen_int_mode (RETURN_ADDR_MASK26, Pmode)) \ - : (arm_arch4 || TARGET_THUMB) ? \ - (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \ + ((arm_arch4 || TARGET_THUMB) \ + ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \ : arm_gen_return_addr_mask ()) diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index dadc228b8ec..dd4b667a279 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -128,11 +128,6 @@ ; patterns that share the same RTL in both ARM and Thumb code. (define_attr "is_thumb" "no,yes" (const (symbol_ref "thumb_code"))) -; PROG_MODE attribute is used to determine whether condition codes are -; clobbered by a call insn: they are if in prog32 mode. This is controlled -; by the -mapcs-{32,26} flag, and possibly the -mcpu=... option. -(define_attr "prog_mode" "prog26,prog32" (const (symbol_ref "arm_prog_mode"))) - ; IS_STRONGARM is set to 'yes' when compiling for StrongARM, it affects ; scheduling decisions for the load unit and the multiplier. (define_attr "is_strongarm" "no,yes" (const (symbol_ref "arm_is_strong"))) @@ -254,8 +249,7 @@ (define_attr "conds" "use,set,clob,jump_clob,nocond" (if_then_else (eq_attr "type" "call") - (if_then_else (eq_attr "prog_mode" "prog32") - (const_string "clob") (const_string "nocond")) + (const_string "clob") (const_string "nocond"))) ; Predicable means that the insn can be conditionally executed based on @@ -3144,16 +3138,12 @@ { if ((TARGET_THUMB || arm_arch4) && GET_CODE (operands[1]) == MEM) { - /* Note: We do not have to worry about TARGET_MMU_TRAPS - here because the insn below will generate an LDRH instruction - rather than an LDR instruction, so we cannot get an unaligned - word access. */ emit_insn (gen_rtx_SET (VOIDmode, operands[0], gen_rtx_ZERO_EXTEND (SImode, operands[1]))); DONE; } - if (TARGET_ARM && TARGET_MMU_TRAPS && GET_CODE (operands[1]) == MEM) + if (TARGET_ARM && GET_CODE (operands[1]) == MEM) { emit_insn (gen_movhi_bytes (operands[0], operands[1])); DONE; @@ -3461,17 +3451,13 @@ } else if (arm_arch4) { - /* Note: We do not have to worry about TARGET_MMU_TRAPS - here because the insn below will generate an LDRH instruction - rather than an LDR instruction, so we cannot get an unaligned - word access. */ emit_insn (gen_rtx_SET (VOIDmode, operands[0], gen_rtx_SIGN_EXTEND (SImode, operands[1]))); DONE; } } - if (TARGET_ARM && TARGET_MMU_TRAPS && GET_CODE (operands[1]) == MEM) + if (TARGET_ARM && GET_CODE (operands[1]) == MEM) { emit_insn (gen_extendhisi2_mem (operands[0], operands[1])); DONE; @@ -4577,89 +4563,40 @@ } else if (!arm_arch4) { - /* Note: We do not have to worry about TARGET_MMU_TRAPS - for v4 and up architectures because LDRH instructions will - be used to access the HI values, and these cannot generate - unaligned word access faults in the MMU. */ if (GET_CODE (operands[1]) == MEM) { - if (TARGET_MMU_TRAPS) - { - rtx base; - rtx offset = const0_rtx; - rtx reg = gen_reg_rtx (SImode); - - if ((GET_CODE (base = XEXP (operands[1], 0)) == REG - || (GET_CODE (base) == PLUS - && (GET_CODE (offset = XEXP (base, 1)) - == CONST_INT) - && ((INTVAL(offset) & 1) != 1) - && GET_CODE (base = XEXP (base, 0)) == REG)) - && REGNO_POINTER_ALIGN (REGNO (base)) >= 32) - { - HOST_WIDE_INT new_offset = INTVAL (offset) & ~3; - rtx new; - - new = gen_rtx_MEM (SImode, - plus_constant (base, new_offset)); - MEM_COPY_ATTRIBUTES (new, operands[1]); - emit_insn (gen_movsi (reg, new)); - if (((INTVAL (offset) & 2) != 0) - ^ (BYTES_BIG_ENDIAN ? 1 : 0)) - { - rtx reg2 = gen_reg_rtx (SImode); - - emit_insn (gen_lshrsi3 (reg2, reg, - GEN_INT (16))); - reg = reg2; - } - } - else - emit_insn (gen_movhi_bytes (reg, operands[1])); - - operands[1] = gen_lowpart (HImode, reg); - } - else if (BYTES_BIG_ENDIAN) + rtx base; + rtx offset = const0_rtx; + rtx reg = gen_reg_rtx (SImode); + + if ((GET_CODE (base = XEXP (operands[1], 0)) == REG + || (GET_CODE (base) == PLUS + && (GET_CODE (offset = XEXP (base, 1)) + == CONST_INT) + && ((INTVAL(offset) & 1) != 1) + && GET_CODE (base = XEXP (base, 0)) == REG)) + && REGNO_POINTER_ALIGN (REGNO (base)) >= 32) { - rtx base; - rtx offset = const0_rtx; - - if ((GET_CODE (base = XEXP (operands[1], 0)) == REG - || (GET_CODE (base) == PLUS - && (GET_CODE (offset = XEXP (base, 1)) - == CONST_INT) - && GET_CODE (base = XEXP (base, 0)) == REG)) - && REGNO_POINTER_ALIGN (REGNO (base)) >= 32) - { - rtx reg = gen_reg_rtx (SImode); - rtx new; - - if ((INTVAL (offset) & 2) == 2) - { - HOST_WIDE_INT new_offset = INTVAL (offset) ^ 2; - new = gen_rtx_MEM (SImode, - plus_constant (base, - new_offset)); - MEM_COPY_ATTRIBUTES (new, operands[1]); - emit_insn (gen_movsi (reg, new)); - } - else - { - new = gen_rtx_MEM (SImode, - XEXP (operands[1], 0)); - MEM_COPY_ATTRIBUTES (new, operands[1]); - emit_insn (gen_rotated_loadsi (reg, new)); - } - - operands[1] = gen_lowpart (HImode, reg); - } - else - { - emit_insn (gen_movhi_bigend (operands[0], - operands[1])); - DONE; - } + HOST_WIDE_INT new_offset = INTVAL (offset) & ~3; + rtx new; + + new = gen_rtx_MEM (SImode, + plus_constant (base, new_offset)); + MEM_COPY_ATTRIBUTES (new, operands[1]); + emit_insn (gen_movsi (reg, new)); + if (((INTVAL (offset) & 2) != 0) + ^ (BYTES_BIG_ENDIAN ? 1 : 0)) + { + rtx reg2 = gen_reg_rtx (SImode); + + emit_insn (gen_lshrsi3 (reg2, reg, GEN_INT (16))); + reg = reg2; + } } + else + emit_insn (gen_movhi_bytes (reg, operands[1])); + + operands[1] = gen_lowpart (HImode, reg); } } } @@ -4762,24 +4699,6 @@ ) -(define_insn "rotated_loadsi" - [(set (match_operand:SI 0 "s_register_operand" "=r") - (rotate:SI (match_operand:SI 1 "offsettable_memory_operand" "o") - (const_int 16)))] - "TARGET_ARM && (!TARGET_MMU_TRAPS)" - "* - { - rtx ops[2]; - - ops[0] = operands[0]; - ops[1] = gen_rtx_MEM (SImode, plus_constant (XEXP (operands[1], 0), 2)); - output_asm_insn (\"ldr%?\\t%0, %1\\t%@ load-rotate\", ops); - return \"\"; - }" - [(set_attr "type" "load1") - (set_attr "predicable" "yes")] -) - (define_expand "movhi_bytes" [(set (match_dup 2) (zero_extend:SI (match_operand:HI 1 "" ""))) (set (match_dup 3) @@ -4851,65 +4770,10 @@ (set_attr "neg_pool_range" "*,*,*,244")] ) -(define_insn "*movhi_insn_littleend" - [(set (match_operand:HI 0 "s_register_operand" "=r,r,r") - (match_operand:HI 1 "general_operand" "rI,K,m"))] - "TARGET_ARM - && !arm_arch4 - && !BYTES_BIG_ENDIAN - && !TARGET_MMU_TRAPS - && (GET_CODE (operands[1]) != CONST_INT - || const_ok_for_arm (INTVAL (operands[1])) - || const_ok_for_arm (~INTVAL (operands[1])))" - "@ - mov%?\\t%0, %1\\t%@ movhi - mvn%?\\t%0, #%B1\\t%@ movhi - ldr%?\\t%0, %1\\t%@ movhi" - [(set_attr "type" "*,*,load1") - (set_attr "predicable" "yes") - (set_attr "pool_range" "4096") - (set_attr "neg_pool_range" "4084")] -) - -(define_insn "*movhi_insn_bigend" - [(set (match_operand:HI 0 "s_register_operand" "=r,r,r") - (match_operand:HI 1 "general_operand" "rI,K,m"))] - "TARGET_ARM - && !arm_arch4 - && BYTES_BIG_ENDIAN - && !TARGET_MMU_TRAPS - && (GET_CODE (operands[1]) != CONST_INT - || const_ok_for_arm (INTVAL (operands[1])) - || const_ok_for_arm (~INTVAL (operands[1])))" - "@ - mov%?\\t%0, %1\\t%@ movhi - mvn%?\\t%0, #%B1\\t%@ movhi - ldr%?\\t%0, %1\\t%@ movhi_bigend\;mov%?\\t%0, %0, asr #16" - [(set_attr "type" "*,*,load1") - (set_attr "predicable" "yes") - (set_attr "length" "4,4,8") - (set_attr "pool_range" "*,*,4092") - (set_attr "neg_pool_range" "*,*,4084")] -) - -(define_insn "*loadhi_si_bigend" - [(set (match_operand:SI 0 "s_register_operand" "=r") - (rotate:SI (subreg:SI (match_operand:HI 1 "memory_operand" "m") 0) - (const_int 16)))] - "TARGET_ARM - && BYTES_BIG_ENDIAN - && !TARGET_MMU_TRAPS" - "ldr%?\\t%0, %1\\t%@ movhi_bigend" - [(set_attr "type" "load1") - (set_attr "predicable" "yes") - (set_attr "pool_range" "4096") - (set_attr "neg_pool_range" "4084")] -) - (define_insn "*movhi_bytes" [(set (match_operand:HI 0 "s_register_operand" "=r,r") (match_operand:HI 1 "arm_rhs_operand" "rI,K"))] - "TARGET_ARM && TARGET_MMU_TRAPS" + "TARGET_ARM" "@ mov%?\\t%0, %1\\t%@ movhi mvn%?\\t%0, #%B1\\t%@ movhi" @@ -4945,7 +4809,7 @@ [(parallel [(match_operand:HI 0 "s_register_operand" "=r") (match_operand:HI 1 "arm_reload_memory_operand" "o") (match_operand:DI 2 "s_register_operand" "=&r")])] - "TARGET_THUMB || (TARGET_ARM && TARGET_MMU_TRAPS)" + "TARGET_EITHER" " if (TARGET_ARM) arm_reload_in_hi (operands); @@ -9324,44 +9188,6 @@ (set_attr "predicable" "yes")] ) -(define_insn "*loadhi_preinc" - [(set (match_operand:HI 3 "s_register_operand" "=r") - (mem:HI (plus:SI (match_operand:SI 1 "s_register_operand" "%0") - (match_operand:SI 2 "index_operand" "rJ")))) - (set (match_operand:SI 0 "s_register_operand" "=r") - (plus:SI (match_dup 1) (match_dup 2)))] - "TARGET_ARM - && !BYTES_BIG_ENDIAN - && !TARGET_MMU_TRAPS - && !arm_arch4 - && REGNO (operands[0]) != FRAME_POINTER_REGNUM - && REGNO (operands[1]) != FRAME_POINTER_REGNUM - && (GET_CODE (operands[2]) != REG - || REGNO (operands[2]) != FRAME_POINTER_REGNUM)" - "ldr%?\\t%3, [%0, %2]!\\t%@ loadhi" - [(set_attr "type" "load_byte") - (set_attr "predicable" "yes")] -) - -(define_insn "*loadhi_predec" - [(set (match_operand:HI 3 "s_register_operand" "=r") - (mem:HI (minus:SI (match_operand:SI 1 "s_register_operand" "0") - (match_operand:SI 2 "s_register_operand" "r")))) - (set (match_operand:SI 0 "s_register_operand" "=r") - (minus:SI (match_dup 1) (match_dup 2)))] - "TARGET_ARM - && !BYTES_BIG_ENDIAN - && !TARGET_MMU_TRAPS - && !arm_arch4 - && REGNO (operands[0]) != FRAME_POINTER_REGNUM - && REGNO (operands[1]) != FRAME_POINTER_REGNUM - && (GET_CODE (operands[2]) != REG - || REGNO (operands[2]) != FRAME_POINTER_REGNUM)" - "ldr%?\\t%3, [%0, -%2]!\\t%@ loadhi" - [(set_attr "type" "load_byte") - (set_attr "predicable" "yes")] -) - (define_insn "*strqi_shiftpreinc" [(set (mem:QI (plus:SI (match_operator:SI 2 "shift_operator" [(match_operand:SI 3 "s_register_operand" "r") @@ -9505,48 +9331,6 @@ [(set_attr "type" "load1") (set_attr "predicable" "yes")]) -(define_insn "*loadhi_shiftpreinc" - [(set (match_operand:HI 5 "s_register_operand" "=r") - (mem:HI (plus:SI (match_operator:SI 2 "shift_operator" - [(match_operand:SI 3 "s_register_operand" "r") - (match_operand:SI 4 "const_shift_operand" "n")]) - (match_operand:SI 1 "s_register_operand" "0")))) - (set (match_operand:SI 0 "s_register_operand" "=r") - (plus:SI (match_op_dup 2 [(match_dup 3) (match_dup 4)]) - (match_dup 1)))] - "TARGET_ARM - && !BYTES_BIG_ENDIAN - && !TARGET_MMU_TRAPS - && !arm_arch4 - && REGNO (operands[0]) != FRAME_POINTER_REGNUM - && REGNO (operands[1]) != FRAME_POINTER_REGNUM - && REGNO (operands[3]) != FRAME_POINTER_REGNUM" - "ldr%?\\t%5, [%0, %3%S2]!\\t%@ loadhi" - [(set_attr "type" "load_byte") - (set_attr "predicable" "yes")] -) - -(define_insn "*loadhi_shiftpredec" - [(set (match_operand:HI 5 "s_register_operand" "=r") - (mem:HI (minus:SI (match_operand:SI 1 "s_register_operand" "0") - (match_operator:SI 2 "shift_operator" - [(match_operand:SI 3 "s_register_operand" "r") - (match_operand:SI 4 "const_shift_operand" "n")])))) - (set (match_operand:SI 0 "s_register_operand" "=r") - (minus:SI (match_dup 1) (match_op_dup 2 [(match_dup 3) - (match_dup 4)])))] - "TARGET_ARM - && !BYTES_BIG_ENDIAN - && !TARGET_MMU_TRAPS - && !arm_arch4 - && REGNO (operands[0]) != FRAME_POINTER_REGNUM - && REGNO (operands[1]) != FRAME_POINTER_REGNUM - && REGNO (operands[3]) != FRAME_POINTER_REGNUM" - "ldr%?\\t%5, [%0, -%3%S2]!\\t%@ loadhi" - [(set_attr "type" "load_byte") - (set_attr "predicable" "yes")] -) - ; It can also support extended post-inc expressions, but combine doesn't ; try these.... ; It doesn't seem worth adding peepholes for anything but the most common @@ -9594,21 +9378,6 @@ "str%?\\t%2, [%0], %1" ) -(define_peephole - [(set (match_operand:HI 0 "s_register_operand" "=r") - (mem:HI (match_operand:SI 1 "s_register_operand" "+r"))) - (set (match_dup 1) - (plus:SI (match_dup 1) (match_operand:SI 2 "index_operand" "rJ")))] - "TARGET_ARM - && !BYTES_BIG_ENDIAN - && !TARGET_MMU_TRAPS - && !arm_arch4 - && REGNO (operands[0]) != REGNO(operands[1]) - && (GET_CODE (operands[2]) != REG - || REGNO(operands[0]) != REGNO (operands[2]))" - "ldr%?\\t%0, [%1], %2\\t%@ loadhi" -) - (define_peephole [(set (match_operand:SI 0 "s_register_operand" "=r") (mem:SI (match_operand:SI 1 "s_register_operand" "+r"))) diff --git a/gcc/config/arm/coff.h b/gcc/config/arm/coff.h index 310c4fba8ec..1be5ea1fa85 100644 --- a/gcc/config/arm/coff.h +++ b/gcc/config/arm/coff.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler. For ARM with COFF object format. - Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2002, 2003 + Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2002, 2003, 2004 Free Software Foundation, Inc. Contributed by Doug Evans (devans@cygnus.com). @@ -31,11 +31,11 @@ #define TARGET_VERSION fputs (" (ARM/coff)", stderr) #undef TARGET_DEFAULT -#define TARGET_DEFAULT (ARM_FLAG_SOFT_FLOAT | ARM_FLAG_APCS_32 | ARM_FLAG_APCS_FRAME) +#define TARGET_DEFAULT (ARM_FLAG_SOFT_FLOAT | ARM_FLAG_APCS_FRAME) #ifndef MULTILIB_DEFAULTS #define MULTILIB_DEFAULTS \ - { "marm", "mlittle-endian", "msoft-float", "mapcs-32", "mno-thumb-interwork" } + { "marm", "mlittle-endian", "msoft-float", "mno-thumb-interwork" } #endif /* This is COFF, but prefer stabs. */ diff --git a/gcc/config/arm/crtn.asm b/gcc/config/arm/crtn.asm index 714060ce60d..3bb9b02e8cb 100644 --- a/gcc/config/arm/crtn.asm +++ b/gcc/config/arm/crtn.asm @@ -1,4 +1,4 @@ -# Copyright (C) 2001 Free Software Foundation, Inc. +# Copyright (C) 2001, 2004 Free Software Foundation, Inc. # Written By Nick Clifton # # This file is free software; you can redistribute it and/or modify it @@ -60,13 +60,9 @@ #if defined __THUMB_INTERWORK__ || defined __thumb__ bx lr -#else -#ifdef __APCS_26__ - movs pc, lr #else mov pc, lr #endif -#endif .endm diff --git a/gcc/config/arm/elf.h b/gcc/config/arm/elf.h index 033403cf160..dae8acdfdf2 100644 --- a/gcc/config/arm/elf.h +++ b/gcc/config/arm/elf.h @@ -108,12 +108,12 @@ #endif #ifndef TARGET_DEFAULT -#define TARGET_DEFAULT (ARM_FLAG_SOFT_FLOAT | ARM_FLAG_APCS_32 | ARM_FLAG_APCS_FRAME) +#define TARGET_DEFAULT (ARM_FLAG_SOFT_FLOAT | ARM_FLAG_APCS_FRAME) #endif #ifndef MULTILIB_DEFAULTS #define MULTILIB_DEFAULTS \ - { "marm", "mlittle-endian", "msoft-float", "mapcs-32", "mno-thumb-interwork", "fno-leading-underscore" } + { "marm", "mlittle-endian", "msoft-float", "mno-thumb-interwork", "fno-leading-underscore" } #endif #define TARGET_ASM_FILE_START_APP_OFF true diff --git a/gcc/config/arm/lib1funcs.asm b/gcc/config/arm/lib1funcs.asm index 7174ed343ad..c36ce4b9d4d 100644 --- a/gcc/config/arm/lib1funcs.asm +++ b/gcc/config/arm/lib1funcs.asm @@ -60,7 +60,7 @@ Boston, MA 02111-1307, USA. */ #define LSYM(x) x #endif -/* Function end macros. Variants for 26 bit APCS and interworking. */ +/* Function end macros. Variants for interworking. */ @ This selects the minimum architecture level required. #define __ARM_ARCH__ 3 @@ -87,12 +87,7 @@ Boston, MA 02111-1307, USA. */ /* How to return from a function call depends on the architecture variant. */ -#ifdef __APCS_26__ - -# define RET movs pc, lr -# define RETc(x) mov##x##s pc, lr - -#elif (__ARM_ARCH__ > 4) || defined(__ARM_ARCH_4T__) +#if (__ARM_ARCH__ > 4) || defined(__ARM_ARCH_4T__) # define RET bx lr # define RETc(x) bx##x lr @@ -112,13 +107,7 @@ Boston, MA 02111-1307, USA. */ /* Don't pass dirn, it's there just to get token pasting right. */ .macro RETLDM regs=, cond=, dirn=ia -#ifdef __APCS_26__ - .ifc "\regs","" - ldm\cond\dirn sp!, {pc}^ - .else - ldm\cond\dirn sp!, {\regs, pc}^ - .endif -#elif defined (__INTERWORKING__) +#if defined (__INTERWORKING__) .ifc "\regs","" ldr\cond lr, [sp], #4 .else diff --git a/gcc/config/arm/linux-elf.h b/gcc/config/arm/linux-elf.h index b4b389c1b7c..616921b20c3 100644 --- a/gcc/config/arm/linux-elf.h +++ b/gcc/config/arm/linux-elf.h @@ -30,9 +30,8 @@ /* Do not assume anything about header files. */ #define NO_IMPLICIT_EXTERN_C -/* Default is to use APCS-32 mode. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT (ARM_FLAG_APCS_32 | ARM_FLAG_MMU_TRAPS) +#define TARGET_DEFAULT (0) #define SUBTARGET_CPU_DEFAULT TARGET_CPU_arm6 @@ -40,9 +39,7 @@ #undef MULTILIB_DEFAULTS #define MULTILIB_DEFAULTS \ - { "marm", "mlittle-endian", "mhard-float", "mapcs-32", "mno-thumb-interwork" } - -#define CPP_APCS_PC_DEFAULT_SPEC "-D__APCS_32__" + { "marm", "mlittle-endian", "mhard-float", "mno-thumb-interwork" } /* The GNU C++ standard library requires that these macros be defined. */ #undef CPLUSPLUS_CPP_SPEC diff --git a/gcc/config/arm/netbsd-elf.h b/gcc/config/arm/netbsd-elf.h index 76bda04f24d..32251bcec54 100644 --- a/gcc/config/arm/netbsd-elf.h +++ b/gcc/config/arm/netbsd-elf.h @@ -35,10 +35,8 @@ /* Default it to use ATPCS with soft-VFP. */ #undef TARGET_DEFAULT #define TARGET_DEFAULT \ - (ARM_FLAG_APCS_32 \ - | ARM_FLAG_SOFT_FLOAT \ + (ARM_FLAG_SOFT_FLOAT \ | ARM_FLAG_APCS_FRAME \ - | ARM_FLAG_MMU_TRAPS \ | TARGET_ENDIAN_DEFAULT) #undef ARM_DEFAULT_ABI diff --git a/gcc/config/arm/netbsd.h b/gcc/config/arm/netbsd.h index 3c82a251900..326fabaf8b2 100644 --- a/gcc/config/arm/netbsd.h +++ b/gcc/config/arm/netbsd.h @@ -35,9 +35,8 @@ /* ARM6 family default cpu. */ #define SUBTARGET_CPU_DEFAULT TARGET_CPU_arm6 -/* Default is to use APCS-32 mode. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT (ARM_FLAG_APCS_32 | ARM_FLAG_SOFT_FLOAT | ARM_FLAG_APCS_FRAME) +#define TARGET_DEFAULT (ARM_FLAG_SOFT_FLOAT | ARM_FLAG_APCS_FRAME) /* Some defines for CPP. arm32 is the NetBSD port name, so we always define arm32 and __arm32__. */ @@ -56,13 +55,9 @@ #undef CPP_SPEC #define CPP_SPEC "\ -%(cpp_cpu_arch) %(cpp_apcs_pc) %(cpp_float) %(cpp_endian) %(netbsd_cpp_spec) \ +%(cpp_cpu_arch) %(cpp_float) %(cpp_endian) %(netbsd_cpp_spec) \ " -/* Because TARGET_DEFAULT sets ARM_FLAG_APCS_32 */ -#undef CPP_APCS_PC_DEFAULT_SPEC -#define CPP_APCS_PC_DEFAULT_SPEC "-D__APCS_32__" - /* Because TARGET_DEFAULT sets ARM_FLAG_SOFT_FLOAT */ #undef CPP_FLOAT_DEFAULT_SPEC #define CPP_FLOAT_DEFAULT_SPEC "-D__SOFTFP__" diff --git a/gcc/config/arm/pe.h b/gcc/config/arm/pe.h index 7fba10b1d06..8eea54ce1f2 100644 --- a/gcc/config/arm/pe.h +++ b/gcc/config/arm/pe.h @@ -1,5 +1,6 @@ /* Definitions of target machine for GNU compiler, for ARM with PE obj format. - Copyright (C) 1995, 1996, 1999, 2000, 2002, 2003 Free Software Foundation, Inc. + Copyright (C) 1995, 1996, 1999, 2000, 2002, 2003, 2004 + Free Software Foundation, Inc. Contributed by Doug Evans (dje@cygnus.com). This file is part of GCC. @@ -65,18 +66,12 @@ N_("Ignore dllimport attribute for functions") }, \ { "no-nop-fun-dllimport", - TARGET_FLAG_NOP_FUN, "" }, -/* Defaulting to APCS-26 support is a legacy issue. It has been done - that way for a long time, so changing it will probably break some - people's worlds. Support for APCS-32 is now enabled as a multilib, - and at some point in the future APCS-32 may become the default. - Possibly when chips that support APCS-26 are no longer made. */ - #undef TARGET_DEFAULT #define TARGET_DEFAULT (ARM_FLAG_SOFT_FLOAT | TARGET_FLAG_NOP_FUN) #undef MULTILIB_DEFAULTS #define MULTILIB_DEFAULTS \ - { "marm", "mlittle-endian", "msoft-float", "mapcs-26", "mno-thumb-interwork" } + { "marm", "mlittle-endian", "msoft-float", "mno-thumb-interwork" } #undef WCHAR_TYPE #define WCHAR_TYPE "short unsigned int" diff --git a/gcc/config/arm/semi.h b/gcc/config/arm/semi.h index 84cf8f6e19d..e30c0fcc326 100644 --- a/gcc/config/arm/semi.h +++ b/gcc/config/arm/semi.h @@ -39,7 +39,7 @@ #endif #ifndef TARGET_DEFAULT -#define TARGET_DEFAULT (ARM_FLAG_APCS_32 | ARM_FLAG_APCS_FRAME) +#define TARGET_DEFAULT (ARM_FLAG_APCS_FRAME) #endif #ifndef SUBTARGET_EXTRA_SPECS @@ -70,6 +70,3 @@ %{mthumb-interwork:-mthumb-interwork} \ %(subtarget_extra_asm_spec)" #endif - -#undef CPP_APCS_PC_DEFAULT_SPEC -#define CPP_APCS_PC_DEFAULT_SPEC "-D__APCS_32__" diff --git a/gcc/config/arm/semiaof.h b/gcc/config/arm/semiaof.h index 41267f36420..8e660836890 100644 --- a/gcc/config/arm/semiaof.h +++ b/gcc/config/arm/semiaof.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler. ARM on semi-hosted platform AOF Syntax assembler. - Copyright (C) 1995, 1996, 1997 Free Software Foundation, Inc. + Copyright (C) 1995, 1996, 1997, 2004 Free Software Foundation, Inc. Contributed by Richard Earnshaw (richard.earnshaw@armltd.co.uk) This file is part of GCC. @@ -26,17 +26,13 @@ builtin_define_std ("semi"); \ } while (0) -#define ASM_SPEC "%{g -g} -arch 4 \ --apcs 3%{mapcs-32:/32bit}%{mapcs-26:/26bit}%{!mapcs-26:%{!macps-32:/32bit}}" +#define ASM_SPEC "%{g -g} -arch 4 -apcs 3/32bit" #define LIB_SPEC "%{Eb: armlib_h.32b%s}%{!Eb: armlib_h.32l%s}" #define TARGET_VERSION fputs (" (ARM/semi-hosted)", stderr); -#define TARGET_DEFAULT ARM_FLAG_APCS_32 +#define TARGET_DEFAULT (0) /* The Norcroft C library defines size_t as "unsigned int". */ #define SIZE_TYPE "unsigned int" - -#undef CPP_APCS_PC_DEFAULT_SPEC -#define CPP_APCS_PC_DEFAULT_SPEC "-D__APCS_32__" diff --git a/gcc/config/arm/t-arm-elf b/gcc/config/arm/t-arm-elf index 3f48f8b81e9..c834220b7fe 100644 --- a/gcc/config/arm/t-arm-elf +++ b/gcc/config/arm/t-arm-elf @@ -13,7 +13,7 @@ MULTILIB_MATCHES = # MULTILIB_OPTIONS += mcpu=ep9312 # MULTILIB_DIRNAMES += ep9312 # MULTILIB_EXCEPTIONS += *mthumb/*mcpu=ep9312* - +# # MULTILIB_OPTIONS += mlittle-endian/mbig-endian # MULTILIB_DIRNAMES += le be # MULTILIB_MATCHES += mbig-endian=mbe mlittle-endian=mle @@ -22,13 +22,8 @@ MULTILIB_MATCHES = # MULTILIB_DIRNAMES += fpu soft # MULTILIB_EXCEPTIONS += *mthumb/*mhard-float* # -# MULTILIB_OPTIONS += mapcs-32/mapcs-26 -# MULTILIB_DIRNAMES += 32bit 26bit -# MULTILIB_EXCEPTIONS += *mthumb/*mapcs-26* -# # MULTILIB_OPTIONS += mno-thumb-interwork/mthumb-interwork # MULTILIB_DIRNAMES += normal interwork -# MULTILIB_EXCEPTIONS += *mapcs-26/*mthumb-interwork* # # MULTILIB_OPTIONS += fno-leading-underscore/fleading-underscore # MULTILIB_DIRNAMES += elf under diff --git a/gcc/config/arm/t-linux b/gcc/config/arm/t-linux index 1c5f48ae6f5..b2697e66e67 100644 --- a/gcc/config/arm/t-linux +++ b/gcc/config/arm/t-linux @@ -9,11 +9,6 @@ LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_lnx # MULTILIB_OPTIONS = mhard-float/msoft-float # MULTILIB_DIRNAMES = hard-float soft-float -# If you want to build both APCS variants as multilib options this is how -# to do it. -# MULTILIB_OPTIONS += mapcs-32/mapcs-26 -# MULTILIB_DIRNAMES += apcs-32 apcs-26 - # EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o # LIBGCC = stmp-multilib diff --git a/gcc/config/arm/t-pe b/gcc/config/arm/t-pe index 4c20b317973..ba4ea10e402 100644 --- a/gcc/config/arm/t-pe +++ b/gcc/config/arm/t-pe @@ -24,8 +24,8 @@ pe.o: $(srcdir)/config/arm/pe.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \ $(RTL_H) output.h flags.h $(TREE_H) expr.h toplev.h $(TM_P_H) $(CC) -c $(ALL_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $(srcdir)/config/arm/pe.c -MULTILIB_OPTIONS = mhard-float mthumb mapcs-32 -MULTILIB_DIRNAMES = fpu thumb apcs32 +MULTILIB_OPTIONS = mhard-float mthumb +MULTILIB_DIRNAMES = fpu thumb LIBGCC = stmp-multilib INSTALL_LIBGCC = install-multilib diff --git a/gcc/config/arm/t-semi b/gcc/config/arm/t-semi index abd642cb02b..f5d8f1a6f5c 100644 --- a/gcc/config/arm/t-semi +++ b/gcc/config/arm/t-semi @@ -29,9 +29,9 @@ dp-bit.c: $(srcdir)/config/fp-bit.c cat $(srcdir)/config/fp-bit.c >> dp-bit.c echo '#endif' >> dp-bit.c -MULTILIB_OPTIONS = msoft-float mapcs-26 mbig-endian mwords-little-endian -MULTILIB_DIRNAMES = soft apcs26 big wlittle -MULTILIB_EXCEPTIONS = *mapcs-26/*mbig-endian* mwords-little-endian *mapcs-26/mwords-little-endian msoft-float/mwords-little-endian +MULTILIB_OPTIONS = msoft-float mbig-endian mwords-little-endian +MULTILIB_DIRNAMES = soft big wlittle +MULTILIB_EXCEPTIONS = mwords-little-endian msoft-float/mwords-little-endian LIBGCC = stmp-multilib INSTALL_LIBGCC = install-multilib diff --git a/gcc/config/arm/t-wince-pe b/gcc/config/arm/t-wince-pe index 9537a7f75ed..c59fc54b89e 100644 --- a/gcc/config/arm/t-wince-pe +++ b/gcc/config/arm/t-wince-pe @@ -24,9 +24,9 @@ pe.o: $(srcdir)/config/arm/pe.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \ $(RTL_H) output.h flags.h $(TREE_H) expr.h toplev.h $(TM_P_H) $(CC) -c $(ALL_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $(srcdir)/config/arm/pe.c -MULTILIB_OPTIONS = mhard-float mapcs-26 -MULTILIB_DIRNAMES = fpu apcs26 -# Note - Thumb multilib omitted because Thumb apcs32 support for +MULTILIB_OPTIONS = mhard-float +MULTILIB_DIRNAMES = fpu +# Note - Thumb multilib omitted because Thumb support for # arm-wince-pe target does not appear to be working in binutils # yet... # MULTILIB_OPTIONS += thumb diff --git a/gcc/config/arm/t-xscale-coff b/gcc/config/arm/t-xscale-coff index 686fd9be7ce..93abfe20450 100644 --- a/gcc/config/arm/t-xscale-coff +++ b/gcc/config/arm/t-xscale-coff @@ -25,7 +25,6 @@ MULTILIB_DIRNAMES = be MULTILIB_EXCEPTIONS = MULTILIB_MATCHES = mbig-endian=mbe mlittle-endian=mle -# Note XScale does not support 26 bit APCS. # Note XScale does not support hard FP MULTILIB_OPTIONS += mthumb-interwork diff --git a/gcc/config/arm/t-xscale-elf b/gcc/config/arm/t-xscale-elf index 1b7119a9553..51c89487c6c 100644 --- a/gcc/config/arm/t-xscale-elf +++ b/gcc/config/arm/t-xscale-elf @@ -25,7 +25,6 @@ MULTILIB_DIRNAMES = be MULTILIB_EXCEPTIONS = MULTILIB_MATCHES = mbig-endian=mbe mlittle-endian=mle -# Note XScale does not support 26 bit APCS. # Note XScale does not support hard FP MULTILIB_OPTIONS += mthumb-interwork diff --git a/gcc/config/arm/uclinux-elf.h b/gcc/config/arm/uclinux-elf.h index e3cd48d4447..4bfb64b8678 100644 --- a/gcc/config/arm/uclinux-elf.h +++ b/gcc/config/arm/uclinux-elf.h @@ -1,5 +1,5 @@ /* Definitions for ARM running ucLinux using ELF - Copyright (C) 1999, 2001 Free Software Foundation, Inc. + Copyright (C) 1999, 2001, 2004 Free Software Foundation, Inc. Contributed by Philip Blundell This file is part of GCC. @@ -27,4 +27,4 @@ #define TARGET_VERSION fputs (" (ARM/ELF ucLinux)", stderr); #undef TARGET_DEFAULT -#define TARGET_DEFAULT (ARM_FLAG_APCS_32 | ARM_FLAG_MMU_TRAPS | ARM_FLAG_SINGLE_PIC_BASE) +#define TARGET_DEFAULT (ARM_FLAG_SINGLE_PIC_BASE) diff --git a/gcc/config/arm/unknown-elf.h b/gcc/config/arm/unknown-elf.h index 573803fce2d..4ef81356162 100644 --- a/gcc/config/arm/unknown-elf.h +++ b/gcc/config/arm/unknown-elf.h @@ -28,9 +28,9 @@ #define TARGET_VERSION fputs (" (ARM/ELF)", stderr); #endif -/* Default to using APCS-32 and software floating point. */ +/* Default to using software floating point. */ #ifndef TARGET_DEFAULT -#define TARGET_DEFAULT (ARM_FLAG_SOFT_FLOAT | ARM_FLAG_APCS_32 | ARM_FLAG_APCS_FRAME) +#define TARGET_DEFAULT (ARM_FLAG_SOFT_FLOAT | ARM_FLAG_APCS_FRAME) #endif /* Now we define the strings used to build the spec file. */ @@ -85,10 +85,6 @@ } \ while (0) -#ifndef CPP_APCS_PC_DEFAULT_SPEC -#define CPP_APCS_PC_DEFAULT_SPEC "-D__APCS_32__" -#endif - #ifndef SUBTARGET_CPU_DEFAULT #define SUBTARGET_CPU_DEFAULT TARGET_CPU_arm7tdmi #endif diff --git a/gcc/config/arm/vxworks.h b/gcc/config/arm/vxworks.h index afe6b7043be..e6db09aa890 100644 --- a/gcc/config/arm/vxworks.h +++ b/gcc/config/arm/vxworks.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GCC, for ARM with targetting the VXWorks run time environment. - Copyright (C) 1999, 2000, 2003 Free Software Foundation, Inc. + Copyright (C) 1999, 2000, 2003, 2004 Free Software Foundation, Inc. Contributed by: Mike Stump Brought up to date by CodeSourcery, LLC. @@ -46,16 +46,16 @@ Boston, MA 02111-1307, USA. */ #undef CC1_SPEC #define CC1_SPEC \ -"%{t4: -mapcs-32 -mlittle-endian -march=armv4 ; \ - t4be: -mapcs-32 -mbig-endian -march=armv4 ; \ +"%{t4: -mlittle-endian -march=armv4 ; \ + t4be: -mbig-endian -march=armv4 ; \ t4t: -mthumb -mthumb-interwork -mlittle-endian -march=armv4t ; \ t4tbe: -mthumb -mthumb-interwork -mbig-endian -march=armv4t ; \ - t5: -mapcs-32 -mlittle-endian -march=armv5 ; \ - t5be: -mapcs-32 -mbig-endian -march=armv5 ; \ + t5: -mlittle-endian -march=armv5 ; \ + t5be: -mbig-endian -march=armv5 ; \ t5t: -mthumb -mthumb-interwork -mlittle-endian -march=armv5 ; \ t5tbe: -mthumb -mthumb-interwork -mbig-endian -march=armv5 ; \ - txscale: -mapcs-32 -mlittle-endian -mcpu=xscale ; \ - txscalebe: -mapcs-32 -mbig-endian -mcpu=xscale ; \ + txscale: -mlittle-endian -mcpu=xscale ; \ + txscalebe: -mbig-endian -mcpu=xscale ; \ : -march=armv4}" /* The -Q options from svr4.h aren't understood and must be removed. */ diff --git a/gcc/config/arm/wince-pe.h b/gcc/config/arm/wince-pe.h index feed1337c90..143ed204b07 100644 --- a/gcc/config/arm/wince-pe.h +++ b/gcc/config/arm/wince-pe.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for ARM with WINCE-PE obj format. - Copyright (C) 2003 Free Software Foundation, Inc. + Copyright (C) 2003, 2004 Free Software Foundation, Inc. Contributed by Nick Clifton This file is part of GCC. @@ -19,11 +19,9 @@ the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* Override arm/pe.h's default apcs26 support. */ - #undef TARGET_DEFAULT -#define TARGET_DEFAULT (ARM_FLAG_APCS_32 | ARM_FLAG_SOFT_FLOAT | TARGET_FLAG_NOP_FUN) +#define TARGET_DEFAULT (ARM_FLAG_SOFT_FLOAT | TARGET_FLAG_NOP_FUN) #undef MULTILIB_DEFAULTS #define MULTILIB_DEFAULTS \ - { "marm", "mlittle-endian", "msoft-float", "mapcs-32", "mno-thumb-interwork" } + { "marm", "mlittle-endian", "msoft-float", "mno-thumb-interwork" } diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 3144fd1fcb4..5b8556634cd 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -386,13 +386,11 @@ in the following sections. @emph{ARM Options} @gccoptlist{-mapcs-frame -mno-apcs-frame @gol -mabi=@var{name} @gol --mapcs-26 -mapcs-32 @gol -mapcs-stack-check -mno-apcs-stack-check @gol -mapcs-float -mno-apcs-float @gol -mapcs-reentrant -mno-apcs-reentrant @gol -msched-prolog -mno-sched-prolog @gol -mlittle-endian -mbig-endian -mwords-little-endian @gol --malignment-traps -mno-alignment-traps @gol -mfloat-abi=@var{name} soft-float -mhard-float -mfpe @gol -mthumb-interwork -mno-thumb-interwork @gol -mcpu=@var{name} -march=@var{name} -mfpu=@var{name} @gol @@ -6791,20 +6789,6 @@ leaf functions. The default is @option{-mno-apcs-frame}. @opindex mapcs This is a synonym for @option{-mapcs-frame}. -@item -mapcs-26 -@opindex mapcs-26 -Generate code for a processor running with a 26-bit program counter, -and conforming to the function calling standards for the APCS 26-bit -option. This option replaces the @option{-m2} and @option{-m3} options -of previous releases of the compiler. - -@item -mapcs-32 -@opindex mapcs-32 -Generate code for a processor running with a 32-bit program counter, -and conforming to the function calling standards for the APCS 32-bit -option. This option replaces the @option{-m6} option of previous releases -of the compiler. - @ignore @c not currently implemented @item -mapcs-stack-check @@ -6901,38 +6885,6 @@ option should only be used if you require compatibility with code for big-endian ARM processors generated by versions of the compiler prior to 2.8. -@item -malignment-traps -@opindex malignment-traps -Generate code that will not trap if the MMU has alignment traps enabled. -On ARM architectures prior to ARMv4, there were no instructions to -access half-word objects stored in memory. However, when reading from -memory a feature of the ARM architecture allows a word load to be used, -even if the address is unaligned, and the processor core will rotate the -data as it is being loaded. This option tells the compiler that such -misaligned accesses will cause a MMU trap and that it should instead -synthesize the access as a series of byte accesses. The compiler can -still use word accesses to load half-word data if it knows that the -address is aligned to a word boundary. - -This option is ignored when compiling for ARM architecture 4 or later, -since these processors have instructions to directly access half-word -objects in memory. - -@item -mno-alignment-traps -@opindex mno-alignment-traps -Generate code that assumes that the MMU will not trap unaligned -accesses. This produces better code when the target instruction set -does not have half-word memory operations (i.e.@: implementations prior to -ARMv4). - -Note that you cannot use this option to access unaligned word objects, -since the processor will only fetch one 32-bit aligned object from -memory. - -The default setting for most targets is @option{-mno-alignment-traps}, since -this produces better code when there are no half-word memory -instructions available. - @item -mshort-load-bytes @itemx -mno-short-load-words @opindex mshort-load-bytes -- 2.30.2