From 61fa72b6553756783166d3fec82a9ef7994b7fe8 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 13 Apr 2015 15:19:34 +0200 Subject: [PATCH] litesata: pep8 (E231) --- misoclib/mem/litesata/core/link/scrambler.py | 8 +- misoclib/mem/litesata/phy/k7/trx.py | 400 +++++++++---------- misoclib/mem/litesata/test/hdd.py | 2 +- 3 files changed, 205 insertions(+), 205 deletions(-) diff --git a/misoclib/mem/litesata/core/link/scrambler.py b/misoclib/mem/litesata/core/link/scrambler.py index 10be3abc..45b01949 100644 --- a/misoclib/mem/litesata/core/link/scrambler.py +++ b/misoclib/mem/litesata/core/link/scrambler.py @@ -26,13 +26,13 @@ class Scrambler(Module): lfsr_coefs = ( (15, 13, 4, 0), #0 (15, 14, 13, 5, 4, 1, 0), - (14, 13, 6, 5, 4, 2,1, 0), - (15, 14, 7, 6, 5, 3,2, 1), + (14, 13, 6, 5, 4, 2, 1, 0), + (15, 14, 7, 6, 5, 3, 2, 1), (13, 8, 7, 6, 3, 2, 0), (14, 9, 8, 7, 4, 3, 1), (15, 10, 9, 8, 5, 4, 2), (15, 13, 11, 10, 9, 6, 5, 4, 3, 0), - (15, 14, 13, 12, 11, 10,7, 6, 5, 1, 0), + (15, 14, 13, 12, 11, 10, 7, 6, 5, 1, 0), (14, 12, 11, 8, 7, 6, 4, 2, 1, 0), (15, 13, 12, 9, 8, 7, 5, 3, 2, 1), (15, 14, 10, 9, 8, 6, 3, 2, 0), @@ -49,7 +49,7 @@ class Scrambler(Module): (15, 13, 12, 6, 5, 4, 0), (15, 14, 7, 6, 5, 4, 1, 0), (13, 8, 7, 6, 5, 4, 2, 1, 0), - (14, 9, 8,7, 6, 5, 3, 2, 1), + (14, 9, 8, 7, 6, 5, 3, 2, 1), (15, 10, 9, 8, 7, 6, 4, 3, 2), (15, 13, 11, 10, 9, 8, 7, 5, 3, 0), (15, 14, 13, 12, 11, 10, 9, 8, 6, 1, 0), diff --git a/misoclib/mem/litesata/phy/k7/trx.py b/misoclib/mem/litesata/phy/k7/trx.py index ad81326f..71eae080 100644 --- a/misoclib/mem/litesata/phy/k7/trx.py +++ b/misoclib/mem/litesata/phy/k7/trx.py @@ -221,272 +221,272 @@ class K7LiteSATAPHYTRX(Module): # Instance gtxe2_channel_parameters = { # Simulation-Only Attributes - "p_SIM_RECEIVER_DETECT_PASS":"TRUE", - "p_SIM_TX_EIDLE_DRIVE_LEVEL":"X", - "p_SIM_RESET_SPEEDUP":"TRUE", - "p_SIM_CPLLREFCLK_SEL":0b001, - "p_SIM_VERSION":"4.0", + "p_SIM_RECEIVER_DETECT_PASS": "TRUE", + "p_SIM_TX_EIDLE_DRIVE_LEVEL": "X", + "p_SIM_RESET_SPEEDUP": "TRUE", + "p_SIM_CPLLREFCLK_SEL": 0b001, + "p_SIM_VERSION": "4.0", # RX Byte and Word Alignment Attributes - "p_ALIGN_COMMA_DOUBLE":"FALSE", - "p_ALIGN_COMMA_ENABLE":ones(10), - "p_ALIGN_COMMA_WORD":2, - "p_ALIGN_MCOMMA_DET":"TRUE", - "p_ALIGN_MCOMMA_VALUE":0b1010000011, - "p_ALIGN_PCOMMA_DET":"TRUE", - "p_ALIGN_PCOMMA_VALUE":0b0101111100, - "p_SHOW_REALIGN_COMMA":"FALSE", - "p_RXSLIDE_AUTO_WAIT":7, - "p_RXSLIDE_MODE":"PCS", - "p_RX_SIG_VALID_DLY":10, + "p_ALIGN_COMMA_DOUBLE": "FALSE", + "p_ALIGN_COMMA_ENABLE": ones(10), + "p_ALIGN_COMMA_WORD": 2, + "p_ALIGN_MCOMMA_DET": "TRUE", + "p_ALIGN_MCOMMA_VALUE": 0b1010000011, + "p_ALIGN_PCOMMA_DET": "TRUE", + "p_ALIGN_PCOMMA_VALUE": 0b0101111100, + "p_SHOW_REALIGN_COMMA": "FALSE", + "p_RXSLIDE_AUTO_WAIT": 7, + "p_RXSLIDE_MODE": "PCS", + "p_RX_SIG_VALID_DLY": 10, # RX 8B/10B Decoder Attributes - "p_RX_DISPERR_SEQ_MATCH":"TRUE", - "p_DEC_MCOMMA_DETECT":"TRUE", - "p_DEC_PCOMMA_DETECT":"TRUE", - "p_DEC_VALID_COMMA_ONLY":"FALSE", + "p_RX_DISPERR_SEQ_MATCH": "TRUE", + "p_DEC_MCOMMA_DETECT": "TRUE", + "p_DEC_PCOMMA_DETECT": "TRUE", + "p_DEC_VALID_COMMA_ONLY": "FALSE", # RX Clock Correction Attributes - "p_CBCC_DATA_SOURCE_SEL":"DECODED", - "p_CLK_COR_SEQ_2_USE":"FALSE", - "p_CLK_COR_KEEP_IDLE":"FALSE", - "p_CLK_COR_MAX_LAT":9, - "p_CLK_COR_MIN_LAT":7, - "p_CLK_COR_PRECEDENCE":"TRUE", - "p_CLK_COR_REPEAT_WAIT":0, - "p_CLK_COR_SEQ_LEN":1, - "p_CLK_COR_SEQ_1_ENABLE":ones(4), - "p_CLK_COR_SEQ_1_1":0b0100000000, - "p_CLK_COR_SEQ_1_2":0b0000000000, - "p_CLK_COR_SEQ_1_3":0b0000000000, - "p_CLK_COR_SEQ_1_4":0b0000000000, - "p_CLK_CORRECT_USE":"FALSE", - "p_CLK_COR_SEQ_2_ENABLE":ones(4), - "p_CLK_COR_SEQ_2_1":0b0100000000, - "p_CLK_COR_SEQ_2_2":0, - "p_CLK_COR_SEQ_2_3":0, - "p_CLK_COR_SEQ_2_4":0, + "p_CBCC_DATA_SOURCE_SEL": "DECODED", + "p_CLK_COR_SEQ_2_USE": "FALSE", + "p_CLK_COR_KEEP_IDLE": "FALSE", + "p_CLK_COR_MAX_LAT": 9, + "p_CLK_COR_MIN_LAT": 7, + "p_CLK_COR_PRECEDENCE": "TRUE", + "p_CLK_COR_REPEAT_WAIT": 0, + "p_CLK_COR_SEQ_LEN": 1, + "p_CLK_COR_SEQ_1_ENABLE": ones(4), + "p_CLK_COR_SEQ_1_1": 0b0100000000, + "p_CLK_COR_SEQ_1_2": 0b0000000000, + "p_CLK_COR_SEQ_1_3": 0b0000000000, + "p_CLK_COR_SEQ_1_4": 0b0000000000, + "p_CLK_CORRECT_USE": "FALSE", + "p_CLK_COR_SEQ_2_ENABLE": ones(4), + "p_CLK_COR_SEQ_2_1": 0b0100000000, + "p_CLK_COR_SEQ_2_2": 0, + "p_CLK_COR_SEQ_2_3": 0, + "p_CLK_COR_SEQ_2_4": 0, # RX Channel Bonding Attributes - "p_CHAN_BOND_KEEP_ALIGN":"FALSE", - "p_CHAN_BOND_MAX_SKEW":1, - "p_CHAN_BOND_SEQ_LEN":1, - "p_CHAN_BOND_SEQ_1_1":0, - "p_CHAN_BOND_SEQ_1_1":0, - "p_CHAN_BOND_SEQ_1_2":0, - "p_CHAN_BOND_SEQ_1_3":0, - "p_CHAN_BOND_SEQ_1_4":0, - "p_CHAN_BOND_SEQ_1_ENABLE":ones(4), - "p_CHAN_BOND_SEQ_2_1":0, - "p_CHAN_BOND_SEQ_2_2":0, - "p_CHAN_BOND_SEQ_2_3":0, - "p_CHAN_BOND_SEQ_2_4":0, - "p_CHAN_BOND_SEQ_2_ENABLE":ones(4), - "p_CHAN_BOND_SEQ_2_USE":"FALSE", - "p_FTS_DESKEW_SEQ_ENABLE":ones(4), - "p_FTS_LANE_DESKEW_CFG":ones(4), - "p_FTS_LANE_DESKEW_EN":"FALSE", + "p_CHAN_BOND_KEEP_ALIGN": "FALSE", + "p_CHAN_BOND_MAX_SKEW": 1, + "p_CHAN_BOND_SEQ_LEN": 1, + "p_CHAN_BOND_SEQ_1_1": 0, + "p_CHAN_BOND_SEQ_1_1": 0, + "p_CHAN_BOND_SEQ_1_2": 0, + "p_CHAN_BOND_SEQ_1_3": 0, + "p_CHAN_BOND_SEQ_1_4": 0, + "p_CHAN_BOND_SEQ_1_ENABLE": ones(4), + "p_CHAN_BOND_SEQ_2_1": 0, + "p_CHAN_BOND_SEQ_2_2": 0, + "p_CHAN_BOND_SEQ_2_3": 0, + "p_CHAN_BOND_SEQ_2_4": 0, + "p_CHAN_BOND_SEQ_2_ENABLE": ones(4), + "p_CHAN_BOND_SEQ_2_USE": "FALSE", + "p_FTS_DESKEW_SEQ_ENABLE": ones(4), + "p_FTS_LANE_DESKEW_CFG": ones(4), + "p_FTS_LANE_DESKEW_EN": "FALSE", # RX Margin Analysis Attributes - "p_ES_CONTROL":0, - "p_ES_ERRDET_EN":"FALSE", - "p_ES_EYE_SCAN_EN":"TRUE", - "p_ES_HORZ_OFFSET":0, - "p_ES_PMA_CFG":0, - "p_ES_PRESCALE":0, - "p_ES_QUALIFIER":0, - "p_ES_QUAL_MASK":0, - "p_ES_SDATA_MASK":0, - "p_ES_VERT_OFFSET":0, + "p_ES_CONTROL": 0, + "p_ES_ERRDET_EN": "FALSE", + "p_ES_EYE_SCAN_EN": "TRUE", + "p_ES_HORZ_OFFSET": 0, + "p_ES_PMA_CFG": 0, + "p_ES_PRESCALE": 0, + "p_ES_QUALIFIER": 0, + "p_ES_QUAL_MASK": 0, + "p_ES_SDATA_MASK": 0, + "p_ES_VERT_OFFSET": 0, # FPGA RX Interface Attributes - "p_RX_DATA_WIDTH":20, + "p_RX_DATA_WIDTH": 20, # PMA Attributes - "p_OUTREFCLK_SEL_INV":0b11, - "p_PMA_RSV":0x00018480, - "p_PMA_RSV2":0x2050, - "p_PMA_RSV3":0, - "p_PMA_RSV4":0, - "p_RX_BIAS_CFG":0b100, - "p_DMONITOR_CFG":0xA00, - "p_RX_CM_SEL":0b11, - "p_RX_CM_TRIM":0b010, - "p_RX_DEBUG_CFG":0, - "p_RX_OS_CFG":0b10000000, - "p_TERM_RCAL_CFG":0, - "p_TERM_RCAL_OVRD":0, - "p_TST_RSV":0, - "p_RX_CLK25_DIV":6, - "p_TX_CLK25_DIV":6, - "p_UCODEER_CLR":0, + "p_OUTREFCLK_SEL_INV": 0b11, + "p_PMA_RSV": 0x00018480, + "p_PMA_RSV2": 0x2050, + "p_PMA_RSV3": 0, + "p_PMA_RSV4": 0, + "p_RX_BIAS_CFG": 0b100, + "p_DMONITOR_CFG": 0xA00, + "p_RX_CM_SEL": 0b11, + "p_RX_CM_TRIM": 0b010, + "p_RX_DEBUG_CFG": 0, + "p_RX_OS_CFG": 0b10000000, + "p_TERM_RCAL_CFG": 0, + "p_TERM_RCAL_OVRD": 0, + "p_TST_RSV": 0, + "p_RX_CLK25_DIV": 6, + "p_TX_CLK25_DIV": 6, + "p_UCODEER_CLR": 0, # PCI Express Attributes - "p_PCS_PCIE_EN":"FALSE", + "p_PCS_PCIE_EN": "FALSE", # PCS Attributes - "p_PCS_RSVD_ATTR":0x100, + "p_PCS_RSVD_ATTR": 0x100, # RX Buffer Attributes - "p_RXBUF_ADDR_MODE":"FAST", - "p_RXBUF_EIDLE_HI_CNT":0b1000, - "p_RXBUF_EIDLE_LO_CNT":0, - "p_RXBUF_EN":"TRUE", - "p_RX_BUFFER_CFG":0, - "p_RXBUF_RESET_ON_CB_CHANGE":"TRUE", - "p_RXBUF_RESET_ON_COMMAALIGN":"FALSE", - "p_RXBUF_RESET_ON_EIDLE":"FALSE", - "p_RXBUF_RESET_ON_RATE_CHANGE":"TRUE", - "p_RXBUFRESET_TIME":1, - "p_RXBUF_THRESH_OVFLW":61, - "p_RXBUF_THRESH_OVRD":"FALSE", - "p_RXBUF_THRESH_UNDFLW":4, - "p_RXDLY_CFG":0x1f, - "p_RXDLY_LCFG":0x30, - "p_RXDLY_TAP_CFG":0, - "p_RXPH_CFG":0, - "p_RXPHDLY_CFG":0x084820, - "p_RXPH_MONITOR_SEL":0, - "p_RX_XCLK_SEL":"RXUSR", - "p_RX_DDI_SEL":0, - "p_RX_DEFER_RESET_BUF_EN":"TRUE", + "p_RXBUF_ADDR_MODE": "FAST", + "p_RXBUF_EIDLE_HI_CNT": 0b1000, + "p_RXBUF_EIDLE_LO_CNT": 0, + "p_RXBUF_EN": "TRUE", + "p_RX_BUFFER_CFG": 0, + "p_RXBUF_RESET_ON_CB_CHANGE": "TRUE", + "p_RXBUF_RESET_ON_COMMAALIGN": "FALSE", + "p_RXBUF_RESET_ON_EIDLE": "FALSE", + "p_RXBUF_RESET_ON_RATE_CHANGE": "TRUE", + "p_RXBUFRESET_TIME": 1, + "p_RXBUF_THRESH_OVFLW": 61, + "p_RXBUF_THRESH_OVRD": "FALSE", + "p_RXBUF_THRESH_UNDFLW": 4, + "p_RXDLY_CFG": 0x1f, + "p_RXDLY_LCFG": 0x30, + "p_RXDLY_TAP_CFG": 0, + "p_RXPH_CFG": 0, + "p_RXPHDLY_CFG": 0x084820, + "p_RXPH_MONITOR_SEL": 0, + "p_RX_XCLK_SEL": "RXUSR", + "p_RX_DDI_SEL": 0, + "p_RX_DEFER_RESET_BUF_EN": "TRUE", #CDR Attributes - "p_RXCDR_CFG":rxcdr_cfg, - "p_RXCDR_FR_RESET_ON_EIDLE":0, - "p_RXCDR_HOLD_DURING_EIDLE":0, - "p_RXCDR_PH_RESET_ON_EIDLE":0, - "p_RXCDR_LOCK_CFG":0b010101, + "p_RXCDR_CFG": rxcdr_cfg, + "p_RXCDR_FR_RESET_ON_EIDLE": 0, + "p_RXCDR_HOLD_DURING_EIDLE": 0, + "p_RXCDR_PH_RESET_ON_EIDLE": 0, + "p_RXCDR_LOCK_CFG": 0b010101, # RX Initialization and Reset Attributes - "p_RXCDRFREQRESET_TIME":1, - "p_RXCDRPHRESET_TIME":1, - "p_RXISCANRESET_TIME":1, - "p_RXPCSRESET_TIME":1, - "p_RXPMARESET_TIME":3, + "p_RXCDRFREQRESET_TIME": 1, + "p_RXCDRPHRESET_TIME": 1, + "p_RXISCANRESET_TIME": 1, + "p_RXPCSRESET_TIME": 1, + "p_RXPMARESET_TIME": 3, # RX OOB Signaling Attributes - "p_RXOOB_CFG":0b0000110, + "p_RXOOB_CFG": 0b0000110, # RX Gearbox Attributes - "p_RXGEARBOX_EN":"FALSE", - "p_GEARBOX_MODE":0, + "p_RXGEARBOX_EN": "FALSE", + "p_GEARBOX_MODE": 0, # PRBS Detection Attribute - "p_RXPRBS_ERR_LOOPBACK":0, + "p_RXPRBS_ERR_LOOPBACK": 0, # Power-Down Attributes - "p_PD_TRANS_TIME_FROM_P2":0x03c, - "p_PD_TRANS_TIME_NONE_P2":0x3c, - "p_PD_TRANS_TIME_TO_P2":0x64, + "p_PD_TRANS_TIME_FROM_P2": 0x03c, + "p_PD_TRANS_TIME_NONE_P2": 0x3c, + "p_PD_TRANS_TIME_TO_P2": 0x64, # RX OOB Signaling Attributes - "p_SAS_MAX_COM":64, - "p_SAS_MIN_COM":36, - "p_SATA_BURST_SEQ_LEN":0b0101, - "p_SATA_BURST_VAL":0b100, - "p_SATA_EIDLE_VAL":0b100, - "p_SATA_MAX_BURST":8, - "p_SATA_MAX_INIT":21, - "p_SATA_MAX_WAKE":7, - "p_SATA_MIN_BURST":4, - "p_SATA_MIN_INIT":12, - "p_SATA_MIN_WAKE":4, + "p_SAS_MAX_COM": 64, + "p_SAS_MIN_COM": 36, + "p_SATA_BURST_SEQ_LEN": 0b0101, + "p_SATA_BURST_VAL": 0b100, + "p_SATA_EIDLE_VAL": 0b100, + "p_SATA_MAX_BURST": 8, + "p_SATA_MAX_INIT": 21, + "p_SATA_MAX_WAKE": 7, + "p_SATA_MIN_BURST": 4, + "p_SATA_MIN_INIT": 12, + "p_SATA_MIN_WAKE": 4, # RX Fabric Clock Output Control Attributes - "p_TRANS_TIME_RATE":0x0e, + "p_TRANS_TIME_RATE": 0x0e, # TX Buffer Attributes - "p_TXBUF_EN":"TRUE", - "p_TXBUF_RESET_ON_RATE_CHANGE":"TRUE", - "p_TXDLY_CFG":0x1f, - "p_TXDLY_LCFG":0x030, - "p_TXDLY_TAP_CFG":0, - "p_TXPH_CFG":0x0780, - "p_TXPHDLY_CFG":0x084020, - "p_TXPH_MONITOR_SEL":0, - "p_TX_XCLK_SEL":"TXOUT", + "p_TXBUF_EN": "TRUE", + "p_TXBUF_RESET_ON_RATE_CHANGE": "TRUE", + "p_TXDLY_CFG": 0x1f, + "p_TXDLY_LCFG": 0x030, + "p_TXDLY_TAP_CFG": 0, + "p_TXPH_CFG": 0x0780, + "p_TXPHDLY_CFG": 0x084020, + "p_TXPH_MONITOR_SEL": 0, + "p_TX_XCLK_SEL": "TXOUT", # FPGA TX Interface Attributes - "p_TX_DATA_WIDTH":20, + "p_TX_DATA_WIDTH": 20, # TX Configurable Driver Attributes - "p_TX_DEEMPH0":0, - "p_TX_DEEMPH1":0, - "p_TX_EIDLE_ASSERT_DELAY":0b110, - "p_TX_EIDLE_DEASSERT_DELAY":0b100, - "p_TX_LOOPBACK_DRIVE_HIZ":"FALSE", - "p_TX_MAINCURSOR_SEL":0, - "p_TX_DRIVE_MODE":"DIRECT", - "p_TX_MARGIN_FULL_0":0b1001110, - "p_TX_MARGIN_FULL_1":0b1001001, - "p_TX_MARGIN_FULL_2":0b1000101, - "p_TX_MARGIN_FULL_3":0b1000010, - "p_TX_MARGIN_FULL_4":0b1000000, - "p_TX_MARGIN_LOW_0":0b1000110, - "p_TX_MARGIN_LOW_1":0b1000100, - "p_TX_MARGIN_LOW_2":0b1000010, - "p_TX_MARGIN_LOW_3":0b1000000, - "p_TX_MARGIN_LOW_4":0b1000000, + "p_TX_DEEMPH0": 0, + "p_TX_DEEMPH1": 0, + "p_TX_EIDLE_ASSERT_DELAY": 0b110, + "p_TX_EIDLE_DEASSERT_DELAY": 0b100, + "p_TX_LOOPBACK_DRIVE_HIZ": "FALSE", + "p_TX_MAINCURSOR_SEL": 0, + "p_TX_DRIVE_MODE": "DIRECT", + "p_TX_MARGIN_FULL_0": 0b1001110, + "p_TX_MARGIN_FULL_1": 0b1001001, + "p_TX_MARGIN_FULL_2": 0b1000101, + "p_TX_MARGIN_FULL_3": 0b1000010, + "p_TX_MARGIN_FULL_4": 0b1000000, + "p_TX_MARGIN_LOW_0": 0b1000110, + "p_TX_MARGIN_LOW_1": 0b1000100, + "p_TX_MARGIN_LOW_2": 0b1000010, + "p_TX_MARGIN_LOW_3": 0b1000000, + "p_TX_MARGIN_LOW_4": 0b1000000, # TX Gearbox Attributes - "p_TXGEARBOX_EN":"FALSE", + "p_TXGEARBOX_EN": "FALSE", # TX Initialization and Reset Attributes - "p_TXPCSRESET_TIME":1, - "p_TXPMARESET_TIME":1, + "p_TXPCSRESET_TIME": 1, + "p_TXPMARESET_TIME": 1, # TX Receiver Detection Attributes - "p_TX_RXDETECT_CFG":0x1832, - "p_TX_RXDETECT_REF":0b100, + "p_TX_RXDETECT_CFG": 0x1832, + "p_TX_RXDETECT_REF": 0b100, # CPLL Attributes - "p_CPLL_CFG":0xBC07DC, - "p_CPLL_FBDIV":4, - "p_CPLL_FBDIV_45":5, - "p_CPLL_INIT_CFG":0x00001e, - "p_CPLL_LOCK_CFG":0x01e8, - "p_CPLL_REFCLK_DIV":1, - "p_RXOUT_DIV":rxout_div, - "p_TXOUT_DIV":txout_div, - "p_SATA_CPLL_CFG":"VCO_3000MHZ", + "p_CPLL_CFG": 0xBC07DC, + "p_CPLL_FBDIV": 4, + "p_CPLL_FBDIV_45": 5, + "p_CPLL_INIT_CFG": 0x00001e, + "p_CPLL_LOCK_CFG": 0x01e8, + "p_CPLL_REFCLK_DIV": 1, + "p_RXOUT_DIV": rxout_div, + "p_TXOUT_DIV": txout_div, + "p_SATA_CPLL_CFG": "VCO_3000MHZ", # RX Initialization and Reset Attributes - "p_RXDFELPMRESET_TIME":0b0001111, + "p_RXDFELPMRESET_TIME": 0b0001111, # RX Equalizer Attributes - "p_RXLPM_HF_CFG":0b00000011110000, - "p_RXLPM_LF_CFG":0b00000011110000, - "p_RX_DFE_GAIN_CFG":0x020fea, - "p_RX_DFE_H2_CFG":0b000000000000, - "p_RX_DFE_H3_CFG":0b000001000000, - "p_RX_DFE_H4_CFG":0b00011110000, - "p_RX_DFE_H5_CFG":0b00011100000, - "p_RX_DFE_KL_CFG":0b0000011111110, - "p_RX_DFE_LPM_CFG":0x0954, - "p_RX_DFE_LPM_HOLD_DURING_EIDLE":0, - "p_RX_DFE_UT_CFG":0b10001111000000000, - "p_RX_DFE_VP_CFG":0b00011111100000011, + "p_RXLPM_HF_CFG": 0b00000011110000, + "p_RXLPM_LF_CFG": 0b00000011110000, + "p_RX_DFE_GAIN_CFG": 0x020fea, + "p_RX_DFE_H2_CFG": 0b000000000000, + "p_RX_DFE_H3_CFG": 0b000001000000, + "p_RX_DFE_H4_CFG": 0b00011110000, + "p_RX_DFE_H5_CFG": 0b00011100000, + "p_RX_DFE_KL_CFG": 0b0000011111110, + "p_RX_DFE_LPM_CFG": 0x0954, + "p_RX_DFE_LPM_HOLD_DURING_EIDLE": 0, + "p_RX_DFE_UT_CFG": 0b10001111000000000, + "p_RX_DFE_VP_CFG": 0b00011111100000011, # Power-Down Attributes - "p_RX_CLKMUX_PD":1, - "p_TX_CLKMUX_PD":1, + "p_RX_CLKMUX_PD": 1, + "p_TX_CLKMUX_PD": 1, # FPGA RX Interface Attribute - "p_RX_INT_DATAWIDTH":0, + "p_RX_INT_DATAWIDTH": 0, # FPGA TX Interface Attribute - "p_TX_INT_DATAWIDTH":0, + "p_TX_INT_DATAWIDTH": 0, # TX Configurable Driver Attributes - "p_TX_QPI_STATUS_EN":0, + "p_TX_QPI_STATUS_EN": 0, # RX Equalizer Attributes - "p_RX_DFE_KL_CFG2":0b00110011000100000001100000001100, - "p_RX_DFE_XYD_CFG":0b0000000000000, + "p_RX_DFE_KL_CFG2": 0b00110011000100000001100000001100, + "p_RX_DFE_XYD_CFG": 0b0000000000000, # TX Configurable Driver Attributes - "p_TX_PREDRIVER_MODE":0, + "p_TX_PREDRIVER_MODE": 0, } self.specials += \ diff --git a/misoclib/mem/litesata/test/hdd.py b/misoclib/mem/litesata/test/hdd.py index 9817aafe..643dfac3 100644 --- a/misoclib/mem/litesata/test/hdd.py +++ b/misoclib/mem/litesata/test/hdd.py @@ -313,7 +313,7 @@ class FIS: else: r = "<<<<<<<<\n" for k in sorted(self.description.keys()): - r += k + " : 0x%x" %getattr(self,k) + "\n" + r += k + " : 0x%x" %getattr(self, k) + "\n" return r -- 2.30.2