From 61faa7c3c443a260eaeb58b111ebd464a2031e06 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Mon, 29 Aug 2022 22:53:52 -0700 Subject: [PATCH] format code --- src/openpower/sv/trans/svp64.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py index 1bb8e697..8550b3b5 100644 --- a/src/openpower/sv/trans/svp64.py +++ b/src/openpower/sv/trans/svp64.py @@ -668,7 +668,7 @@ class SVP64Asm: rm = svp64.instrs[v30b_op] # one row of the svp64 RM CSV else: raise Exception(f"opcode {v30b_op_orig!r} of " - f"{insn!r} not an svp64 instruction") + f"{insn!r} not an svp64 instruction") # get regs info e.g. "RT,RA,RB" v30b_regs = isa_instr.regs[0] @@ -1491,7 +1491,7 @@ if __name__ == '__main__': ] lst = [ 'sv.andi. *80, *80, 1', - 'sv.ffmadds. 6.v, 2.v, 4.v, 6.v', # incorrectly inserted 32-bit op + 'sv.ffmadds. 6.v, 2.v, 4.v, 6.v', # incorrectly inserted 32-bit op 'sv.ffmadds 6.v, 2.v, 4.v, 6.v', # correctly converted to .long ] isa = SVP64Asm(lst, macros=macros) -- 2.30.2