From 620aded541a5b81df74575888754094fea2f2ae2 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Wed, 15 Feb 2017 18:36:21 +0100 Subject: [PATCH] radeonsi: move index buffer flushing into a non-upload indexed case MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit The other codepaths don't need this. Reviewed-by: Nicolai Hähnle --- src/gallium/drivers/radeonsi/si_state_draw.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index d4533093e46..e341f33fb1a 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -1086,16 +1086,15 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info) return; /* info->start will be added by the drawing code */ ib.offset -= start_offset; + } else if (sctx->b.chip_class <= CIK && + r600_resource(ib.buffer)->TC_L2_dirty) { + /* VI reads index buffers through TC L2, so it doesn't + * need this. */ + sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2; + r600_resource(ib.buffer)->TC_L2_dirty = false; } } - /* VI reads index buffers through TC L2. */ - if (info->indexed && sctx->b.chip_class <= CIK && - r600_resource(ib.buffer)->TC_L2_dirty) { - sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2; - r600_resource(ib.buffer)->TC_L2_dirty = false; - } - if (info->indirect) { /* Add the buffer size for memory checking in need_cs_space. */ r600_context_add_resource_size(ctx, info->indirect); -- 2.30.2