From 620b7c900a851526339c265ba6ea9510530de985 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 24 Nov 2013 17:58:05 +0100
Subject: [PATCH] Updated TODOs

---
 README | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/README b/README
index 2277ef129..940689689 100644
--- a/README
+++ b/README
@@ -296,8 +296,7 @@ Roadmap / Large-scale TODOs
    - yosys-bigsim: https://github.com/cliffordwolf/yosys-bigsim
 
 - Technology mapping for real-world applications
-   - Add "mini synth script" feature to techmap pass
-   - Add const-folding via cell parameters to techmap pass
+   - Add bit-wise const-folding via cell parameters to techmap pass
    - Rewrite current stdcells.v techmap rules (modular and clean)
    - Improve Xilinx FGPA synthesis (RAMB, CARRY4, SLR, etc.)
 
-- 
2.30.2