From 620baa6c54b587ed6c647670c00b792b82390174 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 9 Jun 2021 15:43:34 +0000 Subject: [PATCH] pll24_i renamed to clk_24_i --- .../full_core_4_4ksram_litex_ls180_recon.v | 44 +++++++++---------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/experiments9/non_generated/full_core_4_4ksram_litex_ls180_recon.v b/experiments9/non_generated/full_core_4_4ksram_litex_ls180_recon.v index 3988af2..782d303 100644 --- a/experiments9/non_generated/full_core_4_4ksram_litex_ls180_recon.v +++ b/experiments9/non_generated/full_core_4_4ksram_litex_ls180_recon.v @@ -1,13 +1,11 @@ //-------------------------------------------------------------------------------- -// Auto-generated by Migen (7bc4eb1) & LiteX (35929c0f) on 2021-06-09 16:40:53 +// Auto-generated by Migen (7bc4eb1) & LiteX (35929c0f) on 2021-06-09 16:42:55 //-------------------------------------------------------------------------------- module ls180( - input wire uart_tx, - input wire uart_rx, - output wire i2c_scl, - input wire i2c_sda_i, - output wire i2c_sda_o, - output wire i2c_sda_oe, + output wire spimaster_clk, + output wire spimaster_mosi, + output wire spimaster_cs_n, + input wire spimaster_miso, output wire [12:0] sdram_a, input wire [15:0] sdram_dq_i, output wire [15:0] sdram_dq_o, @@ -20,16 +18,18 @@ module ls180( output wire [1:0] sdram_ba, output wire [1:0] sdram_dm, output wire sdram_clock, - output wire spimaster_clk, - output wire spimaster_mosi, - output wire spimaster_cs_n, - input wire spimaster_miso, input wire [15:0] gpio_i, output wire [15:0] gpio_o, output wire [15:0] gpio_oe, input wire eint_0, input wire eint_1, input wire eint_2, + output wire i2c_scl, + input wire i2c_sda_i, + output wire i2c_sda_o, + output wire i2c_sda_oe, + input wire uart_tx, + input wire uart_rx, input wire sys_rst, input wire [1:0] sys_clksel_i, output wire sys_pll_testout_o, @@ -160,12 +160,10 @@ wire main_libresocsim_libresoc_pll_vco_o; wire [1:0] main_libresocsim_libresoc_clk_sel; wire main_libresocsim_libresoc_pll_test_o; wire main_libresocsim_libresoc_pll_24_i; -reg main_libresocsim_libresoc_constraintmanager_uart_tx = 1'd1; -reg main_libresocsim_libresoc_constraintmanager_uart_rx = 1'd0; -wire main_libresocsim_libresoc_constraintmanager_i2c_scl; -wire main_libresocsim_libresoc_constraintmanager_i2c_sda_i; -wire main_libresocsim_libresoc_constraintmanager_i2c_sda_o; -wire main_libresocsim_libresoc_constraintmanager_i2c_sda_oe; +reg main_libresocsim_libresoc_constraintmanager_spimaster_clk = 1'd0; +reg main_libresocsim_libresoc_constraintmanager_spimaster_mosi = 1'd0; +reg main_libresocsim_libresoc_constraintmanager_spimaster_cs_n = 1'd0; +wire main_libresocsim_libresoc_constraintmanager_spimaster_miso; reg [12:0] main_libresocsim_libresoc_constraintmanager_sdram_a = 13'd0; wire [15:0] main_libresocsim_libresoc_constraintmanager_sdram_dq_i; reg [15:0] main_libresocsim_libresoc_constraintmanager_sdram_dq_o = 16'd0; @@ -178,16 +176,18 @@ reg main_libresocsim_libresoc_constraintmanager_sdram_cke = 1'd0; reg [1:0] main_libresocsim_libresoc_constraintmanager_sdram_ba = 2'd0; reg [1:0] main_libresocsim_libresoc_constraintmanager_sdram_dm = 2'd0; reg main_libresocsim_libresoc_constraintmanager_sdram_clock = 1'd0; -reg main_libresocsim_libresoc_constraintmanager_spimaster_clk = 1'd0; -reg main_libresocsim_libresoc_constraintmanager_spimaster_mosi = 1'd0; -reg main_libresocsim_libresoc_constraintmanager_spimaster_cs_n = 1'd0; -wire main_libresocsim_libresoc_constraintmanager_spimaster_miso; wire [15:0] main_libresocsim_libresoc_constraintmanager_gpio_i; reg [15:0] main_libresocsim_libresoc_constraintmanager_gpio_o = 16'd0; reg [15:0] main_libresocsim_libresoc_constraintmanager_gpio_oe = 16'd0; wire main_libresocsim_libresoc_constraintmanager_eint_0; wire main_libresocsim_libresoc_constraintmanager_eint_1; wire main_libresocsim_libresoc_constraintmanager_eint_2; +wire main_libresocsim_libresoc_constraintmanager_i2c_scl; +wire main_libresocsim_libresoc_constraintmanager_i2c_sda_i; +wire main_libresocsim_libresoc_constraintmanager_i2c_sda_o; +wire main_libresocsim_libresoc_constraintmanager_i2c_sda_oe; +reg main_libresocsim_libresoc_constraintmanager_uart_tx = 1'd1; +reg main_libresocsim_libresoc_constraintmanager_uart_rx = 1'd0; reg [29:0] main_libresocsim_interface0_converted_interface_adr = 30'd0; reg [31:0] main_libresocsim_interface0_converted_interface_dat_w = 32'd0; wire [31:0] main_libresocsim_interface0_converted_interface_dat_r; @@ -5817,6 +5817,7 @@ test_issuer test_issuer( .TAP_bus__tdi(main_libresocsim_libresoc_jtag_tdi), .TAP_bus__tms(main_libresocsim_libresoc_jtag_tms), .clk(sys_clk), + .clk_24_i(main_libresocsim_libresoc_pll_24_i), .clk_sel_i(main_libresocsim_libresoc_clk_sel), .core_bigendian_i(1'd0), .dbus__ack(main_libresocsim_libresoc_dbus_ack), @@ -5906,7 +5907,6 @@ test_issuer test_issuer( .mtwi_sda__pad__i(i2c_sda_i), .pc_i(main_libresocsim_libresoc0), .pc_i_ok(1'd0), - .pll_24_i(main_libresocsim_libresoc_pll_24_i), .rst((sys_rst_1 | main_libresocsim_libresoc_reset)), .sdr_a_0__core__o(main_libresocsim_libresoc_constraintmanager_sdram_a[0]), .sdr_a_10__core__o(main_libresocsim_libresoc_constraintmanager_sdram_a[10]), -- 2.30.2