From 623e8e436a4bf044a3cc0ac35e338650b6a90d3a Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 2 Apr 2012 12:59:42 +0200 Subject: [PATCH] fhdl/verilog: do not attempt to initialize instance and mem output signals --- migen/fhdl/verilog.py | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py index f6326e74..fa4c4ae4 100644 --- a/migen/fhdl/verilog.py +++ b/migen/fhdl/verilog.py @@ -220,9 +220,13 @@ def _printmemories(f, ns, handler, clk): r += handler(memory, ns, clk) return r -def _printinit(f, exclude, ns): +def _printinit(f, ios, ns): r = "" - signals = list_signals(f) - exclude - list_targets(f) + signals = list_signals(f) \ + - ios \ + - list_targets(f) \ + - list_inst_ios(f, False, True, False) \ + - list_mem_ios(f, False, True) if signals: r += "initial begin\n" for s in signals: -- 2.30.2