From 624cc417f8c00ada73fd22c65d746584f70dd6c4 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 15 Feb 2022 20:10:05 +0000
Subject: [PATCH] connect up stall signals (fake) for WB Classic compliance

---
 src/ls2.py | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/ls2.py b/src/ls2.py
index 439df0e..7949dda 100644
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -175,6 +175,10 @@ class DDR3SoC(SoC, Elaboratable):
             m.submodules.extcore = self.cpu
             m.submodules.dbuscvt = self.dbusdowncvt
             m.submodules.ibuscvt = self.ibusdowncvt
+            # create stall sigs, assume wishbone classic
+            ibus, dbus = self.cpu.ibus, self.cpu.dbus
+            comb += ibus.stall.eq(ibus.stb & ~ibus.ack)
+            comb += dbus.stall.eq(dbus.stb & ~dbus.ack)
 
         # add blinky lights so we know FPGA is alive
         if platform is not None:
-- 
2.30.2