From 626e172f340ce6e26842b13ee90cef6a0f8c22a4 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 27 May 2021 13:01:42 +0100 Subject: [PATCH] classic wishbone mode: must not do ack if already acked --- src/soc/bus/SPBlock512W64B8W.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/bus/SPBlock512W64B8W.py b/src/soc/bus/SPBlock512W64B8W.py index 994f9626..25f2da74 100644 --- a/src/soc/bus/SPBlock512W64B8W.py +++ b/src/soc/bus/SPBlock512W64B8W.py @@ -59,7 +59,8 @@ class SPBlock512W64B8W(Elaboratable): with m.If(self.enable): # in case of layout problems # wishbone is active if cyc and stb set wb_active = Signal() - m.d.comb += wb_active.eq(self.bus.cyc & self.bus.stb) + m.d.comb += wb_active.eq(self.bus.cyc & self.bus.stb & + ~self.bus.ack) # generate ack (no "pipeline" mode here) m.d.sync += self.bus.ack.eq(wb_active) -- 2.30.2