From 627d53e38be6cfdc2959835376131e45fae5a207 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 22 Oct 2020 18:05:54 +0000
Subject: [PATCH] add non-generated add.il

---
 experiments10/non_generated/add.il | 1705 ++++++++++++++++++++++++++++
 1 file changed, 1705 insertions(+)
 create mode 100644 experiments10/non_generated/add.il

diff --git a/experiments10/non_generated/add.il b/experiments10/non_generated/add.il
new file mode 100644
index 0000000..37b08ae
--- /dev/null
+++ b/experiments10/non_generated/add.il
@@ -0,0 +1,1705 @@
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "add.jtag._fsm"
+module \_fsm
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:24"
+  wire width 1 output 0 \capture
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:23"
+  wire width 1 output 1 \isdr
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:23"
+  wire width 1 \isdr$next
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:25"
+  wire width 1 output 2 \shift
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:26"
+  wire width 1 output 3 \update
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:22"
+  wire width 1 output 4 \isir
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:22"
+  wire width 1 \isir$next
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:28"
+  wire width 1 output 5 \posjtag_rst
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:28"
+  wire width 1 output 6 \posjtag_clk
+  attribute \src "add.py:22"
+  wire width 1 input 7 \tck
+  attribute \src "add.py:22"
+  wire width 1 input 8 \tms
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:49"
+  wire width 1 \local_clk
+  process $group_0
+    assign \posjtag_clk 1'0
+    assign \posjtag_clk \tck
+    sync init
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:36"
+  wire width 1 \rst
+  process $group_1
+    assign \posjtag_rst 1'0
+    assign \posjtag_rst \rst
+    sync init
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:29"
+  wire width 1 \negjtag_clk
+  process $group_2
+    assign \negjtag_clk 1'0
+    assign \negjtag_clk \tck
+    sync init
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:29"
+  wire width 1 \negjtag_rst
+  process $group_3
+    assign \negjtag_rst 1'0
+    assign \negjtag_rst \rst
+    sync init
+  end
+  process $group_4
+    assign \local_clk 1'0
+    assign \local_clk \tck
+    sync init
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:52"
+  wire width 4 \fsm_state
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:52"
+  wire width 4 \fsm_state$next
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:113"
+  wire width 1 $1
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:113"
+  cell $eq $2
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A \fsm_state
+    connect \B 1'0
+    connect \Y $1
+  end
+  process $group_5
+    assign \rst 1'0
+    assign \rst $1
+    sync init
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:114"
+  wire width 1 $3
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:114"
+  cell $eq $4
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 2'10
+    parameter \Y_WIDTH 1'1
+    connect \A \fsm_state
+    connect \B 2'11
+    connect \Y $3
+  end
+  process $group_6
+    assign \capture 1'0
+    assign \capture $3
+    sync init
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:115"
+  wire width 1 $5
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:115"
+  cell $eq $6
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 2'11
+    parameter \Y_WIDTH 1'1
+    connect \A \fsm_state
+    connect \B 3'101
+    connect \Y $5
+  end
+  process $group_7
+    assign \shift 1'0
+    assign \shift $5
+    sync init
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:116"
+  wire width 1 $7
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:116"
+  cell $eq $8
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 1'1
+    connect \A \fsm_state
+    connect \B 4'1000
+    connect \Y $7
+  end
+  process $group_8
+    assign \update 1'0
+    assign \update $7
+    sync init
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:76"
+  wire width 1 $9
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:76"
+  cell $eq $10
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A \tms
+    connect \B 1'0
+    connect \Y $9
+  end
+  process $group_9
+    assign \isir$next \isir
+    attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:52"
+    switch \fsm_state
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:53"
+      attribute \nmigen.decoding "TestLogicReset/0"
+      case 4'0000
+        assign \isir$next 1'0
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:61"
+      attribute \nmigen.decoding "RunTestIdle/1"
+      case 4'0001
+        assign \isir$next 1'0
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:69"
+      attribute \nmigen.decoding "SelectDRScan/2"
+      case 4'0010
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:75"
+      attribute \nmigen.decoding "SelectIRScan/4"
+      case 4'0100
+        attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:76"
+        switch { $9 }
+          attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:76"
+          case 1'1
+            assign \isir$next 1'1
+          attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:79"
+          case
+        end
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:81"
+      attribute \nmigen.decoding "CaptureState/3"
+      case 4'0011
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:86"
+      attribute \nmigen.decoding "ShiftState/5"
+      case 4'0101
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:89"
+      attribute \nmigen.decoding "Exit1/6"
+      case 4'0110
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:94"
+      attribute \nmigen.decoding "Pause/7"
+      case 4'0111
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:97"
+      attribute \nmigen.decoding "Exit2/9"
+      case 4'1001
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:102"
+      attribute \nmigen.decoding "UpdateState/8"
+      case 4'1000
+        assign \isir$next 1'0
+    end
+    sync init
+      update \isir 1'0
+    sync posedge \local_clk
+      update \isir \isir$next
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:70"
+  wire width 1 $11
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:70"
+  cell $eq $12
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A \tms
+    connect \B 1'0
+    connect \Y $11
+  end
+  process $group_10
+    assign \isdr$next \isdr
+    attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:52"
+    switch \fsm_state
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:53"
+      attribute \nmigen.decoding "TestLogicReset/0"
+      case 4'0000
+        assign \isdr$next 1'0
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:61"
+      attribute \nmigen.decoding "RunTestIdle/1"
+      case 4'0001
+        assign \isdr$next 1'0
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:69"
+      attribute \nmigen.decoding "SelectDRScan/2"
+      case 4'0010
+        attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:70"
+        switch { $11 }
+          attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:70"
+          case 1'1
+            assign \isdr$next 1'1
+          attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:73"
+          case
+        end
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:75"
+      attribute \nmigen.decoding "SelectIRScan/4"
+      case 4'0100
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:81"
+      attribute \nmigen.decoding "CaptureState/3"
+      case 4'0011
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:86"
+      attribute \nmigen.decoding "ShiftState/5"
+      case 4'0101
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:89"
+      attribute \nmigen.decoding "Exit1/6"
+      case 4'0110
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:94"
+      attribute \nmigen.decoding "Pause/7"
+      case 4'0111
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:97"
+      attribute \nmigen.decoding "Exit2/9"
+      case 4'1001
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:102"
+      attribute \nmigen.decoding "UpdateState/8"
+      case 4'1000
+        assign \isdr$next 1'0
+    end
+    sync init
+      update \isdr 1'0
+    sync posedge \local_clk
+      update \isdr \isdr$next
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:59"
+  wire width 1 $13
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:59"
+  cell $eq $14
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A \tms
+    connect \B 1'0
+    connect \Y $13
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:67"
+  wire width 1 $15
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:67"
+  cell $eq $16
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A \tms
+    connect \B 1'1
+    connect \Y $15
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:70"
+  wire width 1 $17
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:70"
+  cell $eq $18
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A \tms
+    connect \B 1'0
+    connect \Y $17
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:76"
+  wire width 1 $19
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:76"
+  cell $eq $20
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A \tms
+    connect \B 1'0
+    connect \Y $19
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:82"
+  wire width 1 $21
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:82"
+  cell $eq $22
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A \tms
+    connect \B 1'0
+    connect \Y $21
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:87"
+  wire width 1 $23
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:87"
+  cell $eq $24
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A \tms
+    connect \B 1'1
+    connect \Y $23
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:90"
+  wire width 1 $25
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:90"
+  cell $eq $26
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A \tms
+    connect \B 1'0
+    connect \Y $25
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:95"
+  wire width 1 $27
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:95"
+  cell $eq $28
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A \tms
+    connect \B 1'1
+    connect \Y $27
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:98"
+  wire width 1 $29
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:98"
+  cell $eq $30
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A \tms
+    connect \B 1'0
+    connect \Y $29
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:107"
+  wire width 1 $31
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:107"
+  cell $eq $32
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A \tms
+    connect \B 1'0
+    connect \Y $31
+  end
+  process $group_11
+    assign \fsm_state$next \fsm_state
+    attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:52"
+    switch \fsm_state
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:53"
+      attribute \nmigen.decoding "TestLogicReset/0"
+      case 4'0000
+        attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:59"
+        switch { $13 }
+          attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:59"
+          case 1'1
+            assign \fsm_state$next 4'0001
+        end
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:61"
+      attribute \nmigen.decoding "RunTestIdle/1"
+      case 4'0001
+        attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:67"
+        switch { $15 }
+          attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:67"
+          case 1'1
+            assign \fsm_state$next 4'0010
+        end
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:69"
+      attribute \nmigen.decoding "SelectDRScan/2"
+      case 4'0010
+        attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:70"
+        switch { $17 }
+          attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:70"
+          case 1'1
+            assign \fsm_state$next 4'0011
+          attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:73"
+          case
+            assign \fsm_state$next 4'0100
+        end
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:75"
+      attribute \nmigen.decoding "SelectIRScan/4"
+      case 4'0100
+        attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:76"
+        switch { $19 }
+          attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:76"
+          case 1'1
+            assign \fsm_state$next 4'0011
+          attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:79"
+          case
+            assign \fsm_state$next 4'0000
+        end
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:81"
+      attribute \nmigen.decoding "CaptureState/3"
+      case 4'0011
+        attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:82"
+        switch { $21 }
+          attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:82"
+          case 1'1
+            assign \fsm_state$next 4'0101
+          attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:84"
+          case
+            assign \fsm_state$next 4'0110
+        end
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:86"
+      attribute \nmigen.decoding "ShiftState/5"
+      case 4'0101
+        attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:87"
+        switch { $23 }
+          attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:87"
+          case 1'1
+            assign \fsm_state$next 4'0110
+        end
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:89"
+      attribute \nmigen.decoding "Exit1/6"
+      case 4'0110
+        attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:90"
+        switch { $25 }
+          attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:90"
+          case 1'1
+            assign \fsm_state$next 4'0111
+          attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:92"
+          case
+            assign \fsm_state$next 4'1000
+        end
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:94"
+      attribute \nmigen.decoding "Pause/7"
+      case 4'0111
+        attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:95"
+        switch { $27 }
+          attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:95"
+          case 1'1
+            assign \fsm_state$next 4'1001
+        end
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:97"
+      attribute \nmigen.decoding "Exit2/9"
+      case 4'1001
+        attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:98"
+        switch { $29 }
+          attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:98"
+          case 1'1
+            assign \fsm_state$next 4'0101
+          attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:100"
+          case
+            assign \fsm_state$next 4'1000
+        end
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:102"
+      attribute \nmigen.decoding "UpdateState/8"
+      case 4'1000
+        attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:107"
+        switch { $31 }
+          attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:107"
+          case 1'1
+            assign \fsm_state$next 4'0001
+          attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:109"
+          case
+            assign \fsm_state$next 4'0010
+        end
+    end
+    sync init
+      update \fsm_state 4'0000
+    sync posedge \local_clk
+      update \fsm_state \fsm_state$next
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "add.jtag._irblock"
+module \_irblock
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:127"
+  wire width 4 output 0 \ir
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:127"
+  wire width 4 \ir$next
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:24"
+  wire width 1 input 1 \capture
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:25"
+  wire width 1 input 2 \shift
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:26"
+  wire width 1 input 3 \update
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:22"
+  wire width 1 input 4 \isir
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:128"
+  wire width 1 output 5 \tdo
+  attribute \src "add.py:22"
+  wire width 1 input 6 \tdi
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:28"
+  wire width 1 input 7 \posjtag_rst
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:28"
+  wire width 1 input 8 \posjtag_clk
+  process $group_0
+    assign \tdo 1'0
+    assign \tdo \ir [0]
+    sync init
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:138"
+  wire width 4 \shift_ir
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:138"
+  wire width 4 \shift_ir$next
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:366"
+  wire width 1 $1
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:366"
+  cell $and $2
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A \isir
+    connect \B \capture
+    connect \Y $1
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:367"
+  wire width 1 $3
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:367"
+  cell $and $4
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A \isir
+    connect \B \shift
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:368"
+  wire width 1 $5
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:368"
+  cell $and $6
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A \isir
+    connect \B \update
+    connect \Y $5
+  end
+  process $group_1
+    assign \shift_ir$next \shift_ir
+    attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:141"
+    switch { $5 $3 $1 }
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:141"
+      case 3'--1
+        assign \shift_ir$next \ir
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:143"
+      case 3'-1-
+        assign \shift_ir$next { \tdi \shift_ir [3:1] }
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:145"
+      case 3'1--
+    end
+    sync init
+      update \shift_ir 4'0000
+    sync posedge \posjtag_clk
+      update \shift_ir \shift_ir$next
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:366"
+  wire width 1 $7
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:366"
+  cell $and $8
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A \isir
+    connect \B \capture
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:367"
+  wire width 1 $9
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:367"
+  cell $and $10
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A \isir
+    connect \B \shift
+    connect \Y $9
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:368"
+  wire width 1 $11
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:368"
+  cell $and $12
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A \isir
+    connect \B \update
+    connect \Y $11
+  end
+  process $group_2
+    assign \ir$next \ir
+    attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:141"
+    switch { $11 $9 $7 }
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:141"
+      case 3'--1
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:143"
+      case 3'-1-
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:145"
+      case 3'1--
+        assign \ir$next \shift_ir
+    end
+    attribute \src "/home/lkcl/nmigen/nmigen/hdl/xfrm.py:530"
+    switch \posjtag_rst
+      case 1'1
+        assign \ir$next 4'0001
+    end
+    sync init
+      update \ir 4'0001
+    sync posedge \posjtag_clk
+      update \ir \ir$next
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "add.jtag._idblock"
+module \_idblock
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:127"
+  wire width 4 input 0 \ir
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:24"
+  wire width 1 input 1 \capture
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:23"
+  wire width 1 input 2 \isdr
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:25"
+  wire width 1 input 3 \shift
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:26"
+  wire width 1 input 4 \update
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:225"
+  wire width 1 output 5 \jtag_id_tdo
+  attribute \src "add.py:22"
+  wire width 1 input 6 \tdi
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:28"
+  wire width 1 input 7 \posjtag_rst
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:28"
+  wire width 1 input 8 \posjtag_clk
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:239"
+  wire width 1 \_tdi
+  process $group_0
+    assign \_tdi 1'0
+    assign \_tdi \tdi
+    sync init
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:240"
+  wire width 1 \_capture
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
+  wire width 1 $1
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
+  cell $eq $2
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A \ir
+    connect \B 1'1
+    connect \Y $1
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
+  wire width 1 $3
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
+  cell $eq $4
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 1'1
+    connect \A \ir
+    connect \B 4'1111
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
+  wire width 1 $5
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
+  cell $or $6
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A $1
+    connect \B $3
+    connect \Y $5
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
+  wire width 1 $7
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
+  cell $and $8
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A \isdr
+    connect \B $5
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:379"
+  wire width 1 $9
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:379"
+  cell $and $10
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A $7
+    connect \B \capture
+    connect \Y $9
+  end
+  process $group_1
+    assign \_capture 1'0
+    assign \_capture $9
+    sync init
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:241"
+  wire width 1 \_shift
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
+  wire width 1 $11
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
+  cell $eq $12
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A \ir
+    connect \B 1'1
+    connect \Y $11
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
+  wire width 1 $13
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
+  cell $eq $14
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 1'1
+    connect \A \ir
+    connect \B 4'1111
+    connect \Y $13
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
+  wire width 1 $15
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
+  cell $or $16
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A $11
+    connect \B $13
+    connect \Y $15
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
+  wire width 1 $17
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
+  cell $and $18
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A \isdr
+    connect \B $15
+    connect \Y $17
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:380"
+  wire width 1 $19
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:380"
+  cell $and $20
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A $17
+    connect \B \shift
+    connect \Y $19
+  end
+  process $group_2
+    assign \_shift 1'0
+    assign \_shift $19
+    sync init
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:242"
+  wire width 1 \_update
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
+  wire width 1 $21
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
+  cell $eq $22
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A \ir
+    connect \B 1'1
+    connect \Y $21
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
+  wire width 1 $23
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
+  cell $eq $24
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 1'1
+    connect \A \ir
+    connect \B 4'1111
+    connect \Y $23
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
+  wire width 1 $25
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
+  cell $or $26
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A $21
+    connect \B $23
+    connect \Y $25
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
+  wire width 1 $27
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
+  cell $and $28
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A \isdr
+    connect \B $25
+    connect \Y $27
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:381"
+  wire width 1 $29
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:381"
+  cell $and $30
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A $27
+    connect \B \update
+    connect \Y $29
+  end
+  process $group_3
+    assign \_update 1'0
+    assign \_update $29
+    sync init
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:243"
+  wire width 1 \_bypass
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:382"
+  wire width 1 $31
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:382"
+  cell $eq $32
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 1'1
+    connect \A \ir
+    connect \B 4'1111
+    connect \Y $31
+  end
+  process $group_4
+    assign \_bypass 1'0
+    assign \_bypass $31
+    sync init
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:236"
+  wire width 32 \jtag_id_sr
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:236"
+  wire width 32 \jtag_id_sr$next
+  process $group_5
+    assign \jtag_id_tdo 1'0
+    assign \jtag_id_tdo \jtag_id_sr [0]
+    sync init
+  end
+  process $group_6
+    assign \jtag_id_sr$next \jtag_id_sr
+    attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:254"
+    switch { \_shift \_capture }
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:254"
+      case 2'-1
+        assign \jtag_id_sr$next { 4'0000 16'0000000000000001 11'10001111111 1'1 }
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:256"
+      case 2'1-
+        attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:257"
+        switch { \_bypass }
+          attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:257"
+          case 1'1
+            assign \jtag_id_sr$next [0] \_tdi
+          attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:259"
+          case
+            assign \jtag_id_sr$next { \_tdi \jtag_id_sr [31:1] }
+        end
+    end
+    sync init
+      update \jtag_id_sr 32'00000000000000000000000000000000
+    sync posedge \posjtag_clk
+      update \jtag_id_sr \jtag_id_sr$next
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "add.jtag"
+module \jtag
+  attribute \src "/home/lkcl/nmigen/nmigen/hdl/ir.py:526"
+  wire width 1 input 0 \rst
+  attribute \src "/home/lkcl/nmigen/nmigen/hdl/ir.py:526"
+  wire width 1 input 1 \clk
+  attribute \src "add.py:22"
+  wire width 1 input 2 \tdi
+  attribute \src "add.py:22"
+  wire width 1 output 3 \tdo
+  attribute \src "add.py:22"
+  wire width 1 input 4 \tck
+  attribute \src "add.py:22"
+  wire width 1 input 5 \tms
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:28"
+  wire width 1 \posjtag_clk
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:28"
+  wire width 1 \posjtag_rst
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:24"
+  wire width 1 \_fsm_capture
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:23"
+  wire width 1 \_fsm_isdr
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:25"
+  wire width 1 \_fsm_shift
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:26"
+  wire width 1 \_fsm_update
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:22"
+  wire width 1 \_fsm_isir
+  cell \_fsm \_fsm
+    connect \capture \_fsm_capture
+    connect \isdr \_fsm_isdr
+    connect \shift \_fsm_shift
+    connect \update \_fsm_update
+    connect \isir \_fsm_isir
+    connect \posjtag_rst \posjtag_rst
+    connect \posjtag_clk \posjtag_clk
+    connect \tck \tck
+    connect \tms \tms
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:127"
+  wire width 4 \_irblock_ir
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:128"
+  wire width 1 \_irblock_tdo
+  cell \_irblock \_irblock
+    connect \ir \_irblock_ir
+    connect \capture \_fsm_capture
+    connect \shift \_fsm_shift
+    connect \update \_fsm_update
+    connect \isir \_fsm_isir
+    connect \tdo \_irblock_tdo
+    connect \tdi \tdi
+    connect \posjtag_rst \posjtag_rst
+    connect \posjtag_clk \posjtag_clk
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:225"
+  wire width 1 \_idblock_jtag_id_tdo
+  cell \_idblock \_idblock
+    connect \ir \_irblock_ir
+    connect \capture \_fsm_capture
+    connect \isdr \_fsm_isdr
+    connect \shift \_fsm_shift
+    connect \update \_fsm_update
+    connect \jtag_id_tdo \_idblock_jtag_id_tdo
+    connect \tdi \tdi
+    connect \posjtag_rst \posjtag_rst
+    connect \posjtag_clk \posjtag_clk
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:387"
+  wire width 1 \io_capture
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392"
+  wire width 1 $1
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392"
+  cell $eq $2
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A \_irblock_ir
+    connect \B 1'0
+    connect \Y $1
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392"
+  wire width 1 $3
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392"
+  cell $eq $4
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 2'10
+    parameter \Y_WIDTH 1'1
+    connect \A \_irblock_ir
+    connect \B 2'10
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392"
+  wire width 1 $5
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392"
+  cell $or $6
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A $1
+    connect \B $3
+    connect \Y $5
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
+  wire width 1 $7
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:396"
+  cell $and $8
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A $5
+    connect \B \_fsm_capture
+    connect \Y $7
+  end
+  process $group_0
+    assign \io_capture 1'0
+    assign \io_capture $7
+    sync init
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:388"
+  wire width 1 \io_shift
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392"
+  wire width 1 $9
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392"
+  cell $eq $10
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A \_irblock_ir
+    connect \B 1'0
+    connect \Y $9
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392"
+  wire width 1 $11
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392"
+  cell $eq $12
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 2'10
+    parameter \Y_WIDTH 1'1
+    connect \A \_irblock_ir
+    connect \B 2'10
+    connect \Y $11
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392"
+  wire width 1 $13
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392"
+  cell $or $14
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A $9
+    connect \B $11
+    connect \Y $13
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:393"
+  wire width 1 $15
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:393"
+  cell $eq $16
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 2'10
+    parameter \Y_WIDTH 1'1
+    connect \A \_irblock_ir
+    connect \B 2'10
+    connect \Y $15
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:394"
+  wire width 1 $17
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:394"
+  cell $or $18
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A $13
+    connect \B $15
+    connect \Y $17
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:394"
+  wire width 1 $19
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:394"
+  cell $and $20
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A \_fsm_isdr
+    connect \B $17
+    connect \Y $19
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:398"
+  wire width 1 $21
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:398"
+  cell $and $22
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A $19
+    connect \B \_fsm_shift
+    connect \Y $21
+  end
+  process $group_1
+    assign \io_shift 1'0
+    assign \io_shift $21
+    sync init
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:389"
+  wire width 1 \io_update
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392"
+  wire width 1 $23
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392"
+  cell $eq $24
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A \_irblock_ir
+    connect \B 1'0
+    connect \Y $23
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392"
+  wire width 1 $25
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392"
+  cell $eq $26
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 2'10
+    parameter \Y_WIDTH 1'1
+    connect \A \_irblock_ir
+    connect \B 2'10
+    connect \Y $25
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392"
+  wire width 1 $27
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:392"
+  cell $or $28
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A $23
+    connect \B $25
+    connect \Y $27
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:393"
+  wire width 1 $29
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:393"
+  cell $eq $30
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 2'10
+    parameter \Y_WIDTH 1'1
+    connect \A \_irblock_ir
+    connect \B 2'10
+    connect \Y $29
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:394"
+  wire width 1 $31
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:394"
+  cell $or $32
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A $27
+    connect \B $29
+    connect \Y $31
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:394"
+  wire width 1 $33
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:394"
+  cell $and $34
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A \_fsm_isdr
+    connect \B $31
+    connect \Y $33
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:399"
+  wire width 1 $35
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:399"
+  cell $and $36
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A $33
+    connect \B \_fsm_update
+    connect \Y $35
+  end
+  process $group_2
+    assign \io_update 1'0
+    assign \io_update $35
+    sync init
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:390"
+  wire width 1 \io_bd2io
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:400"
+  wire width 1 $37
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:400"
+  cell $eq $38
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A \_irblock_ir
+    connect \B 1'0
+    connect \Y $37
+  end
+  process $group_3
+    assign \io_bd2io 1'0
+    assign \io_bd2io $37
+    sync init
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:391"
+  wire width 1 \io_bd2core
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:401"
+  wire width 1 $39
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:401"
+  cell $eq $40
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A \_irblock_ir
+    connect \B 1'0
+    connect \Y $39
+  end
+  process $group_4
+    assign \io_bd2core 1'0
+    assign \io_bd2core $39
+    sync init
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:410"
+  wire width 1 \jtag_tdo
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
+  wire width 1 $41
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
+  cell $eq $42
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A \_irblock_ir
+    connect \B 1'1
+    connect \Y $41
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
+  wire width 1 $43
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
+  cell $eq $44
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 1'1
+    connect \A \_irblock_ir
+    connect \B 4'1111
+    connect \Y $43
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
+  wire width 1 $45
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
+  cell $or $46
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A $41
+    connect \B $43
+    connect \Y $45
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
+  wire width 1 $47
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:374"
+  cell $and $48
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A \_fsm_isdr
+    connect \B $45
+    connect \Y $47
+  end
+  process $group_5
+    assign \jtag_tdo 1'0
+    attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:411"
+    switch { $47 \_fsm_isir }
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:411"
+      case 2'-1
+        assign \jtag_tdo \_irblock_tdo
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:413"
+      case 2'1-
+        assign \jtag_tdo \_idblock_jtag_id_tdo
+    end
+    sync init
+  end
+  attribute \src "add.py:29"
+  wire width 3 \sr0__o
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:638"
+  wire width 3 \sr0_reg
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:638"
+  wire width 3 \sr0_reg$next
+  process $group_6
+    assign \sr0__o 3'000
+    assign \sr0__o \sr0_reg
+    sync init
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:641"
+  wire width 1 \sr0_isir
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:646"
+  wire width 1 $49
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:646"
+  cell $eq $50
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 2'11
+    parameter \Y_WIDTH 1'1
+    connect \A \_irblock_ir
+    connect \B 3'100
+    connect \Y $49
+  end
+  process $group_7
+    assign \sr0_isir 1'0
+    assign \sr0_isir { $49 }
+    sync init
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:642"
+  wire width 1 \sr0_capture
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:647"
+  wire width 1 $51
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:647"
+  cell $ne $52
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A \sr0_isir
+    connect \B 1'0
+    connect \Y $51
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:647"
+  wire width 1 $53
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:647"
+  cell $and $54
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A $51
+    connect \B \_fsm_capture
+    connect \Y $53
+  end
+  process $group_8
+    assign \sr0_capture 1'0
+    assign \sr0_capture $53
+    sync init
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:643"
+  wire width 1 \sr0_shift
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:648"
+  wire width 1 $55
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:648"
+  cell $ne $56
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A \sr0_isir
+    connect \B 1'0
+    connect \Y $55
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:648"
+  wire width 1 $57
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:648"
+  cell $and $58
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A $55
+    connect \B \_fsm_shift
+    connect \Y $57
+  end
+  process $group_9
+    assign \sr0_shift 1'0
+    assign \sr0_shift $57
+    sync init
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:644"
+  wire width 1 \sr0_update
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:649"
+  wire width 1 $59
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:649"
+  cell $ne $60
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A \sr0_isir
+    connect \B 1'0
+    connect \Y $59
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:649"
+  wire width 1 $61
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:649"
+  cell $and $62
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A $59
+    connect \B \_fsm_update
+    connect \Y $61
+  end
+  process $group_10
+    assign \sr0_update 1'0
+    assign \sr0_update $61
+    sync init
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:656"
+  wire width 1 \sr0_update_core
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:656"
+  wire width 1 \sr0_update_core$next
+  process $group_11
+    assign \sr0_update_core$next \sr0_update_core
+    assign \sr0_update_core$next \sr0_update
+    attribute \src "/home/lkcl/nmigen/nmigen/hdl/xfrm.py:530"
+    switch \rst
+      case 1'1
+        assign \sr0_update_core$next 1'0
+    end
+    sync init
+      update \sr0_update_core 1'0
+    sync posedge \clk
+      update \sr0_update_core \sr0_update_core$next
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:657"
+  wire width 1 \sr0_update_core_prev
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:657"
+  wire width 1 \sr0_update_core_prev$next
+  process $group_12
+    assign \sr0_update_core_prev$next \sr0_update_core_prev
+    assign \sr0_update_core_prev$next \sr0_update_core
+    attribute \src "/home/lkcl/nmigen/nmigen/hdl/xfrm.py:530"
+    switch \rst
+      case 1'1
+        assign \sr0_update_core_prev$next 1'0
+    end
+    sync init
+      update \sr0_update_core_prev 1'0
+    sync posedge \clk
+      update \sr0_update_core_prev \sr0_update_core_prev$next
+  end
+  attribute \src "add.py:29"
+  wire width 1 \sr0__oe
+  attribute \src "add.py:29"
+  wire width 1 \sr0__oe$next
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:663"
+  wire width 1 $63
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:663"
+  cell $not $64
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A \sr0_update_core
+    connect \Y $63
+  end
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:663"
+  wire width 1 $65
+  attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:663"
+  cell $and $66
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 1'1
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 1'1
+    connect \A \sr0_update_core_prev
+    connect \B $63
+    connect \Y $65
+  end
+  process $group_13
+    assign \sr0__oe$next \sr0__oe
+    attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:663"
+    switch { $65 }
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:663"
+      case 1'1
+        assign \sr0__oe$next \sr0_isir
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:666"
+      case
+        assign \sr0__oe$next 1'0
+    end
+    attribute \src "/home/lkcl/nmigen/nmigen/hdl/xfrm.py:530"
+    switch \rst
+      case 1'1
+        assign \sr0__oe$next 1'0
+    end
+    sync init
+      update \sr0__oe 1'0
+    sync posedge \clk
+      update \sr0__oe \sr0__oe$next
+  end
+  attribute \src "add.py:29"
+  wire width 3 \sr0__i
+  process $group_14
+    assign \sr0_reg$next \sr0_reg
+    attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:669"
+    switch { \sr0_shift }
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:669"
+      case 1'1
+        assign \sr0_reg$next { \tdi \sr0_reg [2:1] }
+    end
+    attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:671"
+    switch { \sr0_capture }
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:671"
+      case 1'1
+        assign \sr0_reg$next \sr0__i
+    end
+    attribute \src "/home/lkcl/nmigen/nmigen/hdl/xfrm.py:530"
+    switch \posjtag_rst
+      case 1'1
+        assign \sr0_reg$next 3'000
+    end
+    sync init
+      update \sr0_reg 3'000
+    sync posedge \posjtag_clk
+      update \sr0_reg \sr0_reg$next
+  end
+  process $group_15
+    assign \tdo 1'0
+    attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:681"
+    switch { \sr0_shift }
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:681"
+      case 1'1
+        assign \tdo \sr0_reg [0]
+      attribute \src "/home/lkcl/c4m-jtag/c4m/nmigen/jtag/tap.py:688"
+      case
+        assign \tdo \jtag_tdo
+    end
+    sync init
+  end
+  connect \sr0__i 3'000
+end
+attribute \generator "nMigen"
+attribute \top 1
+attribute \nmigen.hierarchy "add"
+module \add
+  attribute \src "add.py:17"
+  wire width 4 input 0 \a
+  attribute \src "add.py:18"
+  wire width 4 input 1 \b
+  attribute \src "add.py:19"
+  wire width 4 output 2 \f
+  attribute \src "add.py:19"
+  wire width 4 \f$next
+  attribute \src "add.py:22"
+  wire width 1 input 3 \tck
+  attribute \src "add.py:22"
+  wire width 1 input 4 \tms
+  attribute \src "add.py:22"
+  wire width 1 output 5 \tdo
+  attribute \src "add.py:22"
+  wire width 1 input 6 \tdi
+  attribute \src "/home/lkcl/nmigen/nmigen/hdl/ir.py:526"
+  wire width 1 input 7 \clk
+  attribute \src "/home/lkcl/nmigen/nmigen/hdl/ir.py:526"
+  wire width 1 input 8 \rst
+  cell \jtag \jtag
+    connect \rst \rst
+    connect \clk \clk
+    connect \tdi \tdi
+    connect \tdo \tdo
+    connect \tck \tck
+    connect \tms \tms
+  end
+  attribute \src "add.py:38"
+  wire width 5 $1
+  attribute \src "add.py:38"
+  wire width 5 $2
+  attribute \src "add.py:38"
+  cell $add $3
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 3'100
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 3'100
+    parameter \Y_WIDTH 3'101
+    connect \A \a
+    connect \B \b
+    connect \Y $2
+  end
+  connect $1 $2
+  process $group_0
+    assign \f$next \f
+    assign \f$next $1 [3:0]
+    attribute \src "/home/lkcl/nmigen/nmigen/hdl/xfrm.py:530"
+    switch \rst
+      case 1'1
+        assign \f$next 4'0000
+    end
+    sync init
+      update \f 4'0000
+    sync posedge \clk
+      update \f \f$next
+  end
+end
-- 
2.30.2