From 6297772a2e0825c30fc826e59d2fafd20876d5df Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 16 May 2020 23:50:52 +0100 Subject: [PATCH] formatting --- 3d_gpu/architecture/tomasulo_transformation.mdwn | 2 -- 1 file changed, 2 deletions(-) diff --git a/3d_gpu/architecture/tomasulo_transformation.mdwn b/3d_gpu/architecture/tomasulo_transformation.mdwn index 3622a21a4..a93113bcb 100644 --- a/3d_gpu/architecture/tomasulo_transformation.mdwn +++ b/3d_gpu/architecture/tomasulo_transformation.mdwn @@ -2,7 +2,6 @@ See [discussion](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-May/006747.html) -''' On Saturday, May 16, 2020, Yehowshua wrote: > This is a very intricate and complicated subject matter for sure. @@ -130,4 +129,3 @@ proper stratification and design of the register files, massive Vector parallelism at the pipelines would be kept fully occupied without an overwhelming increase in gates or power consumption that would normally be expected, and scalar performance would be similarly high as well. -''' -- 2.30.2