From 62e5ff9ba8ce9711317f97efdb9810491aaa4f06 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 19 Feb 2019 16:06:03 -0800 Subject: [PATCH] abc9 to cope with indexed wires when creating $lut from $_NOT_ --- passes/techmap/abc9.cc | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index f63b69acd..e85cf48e1 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -597,7 +597,12 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri // Otherwise, clone the driving LUT to guarantee that we // won't increase the max logic depth // (TODO: Optimise by not cloning unless will increase depth) - RTLIL::Cell* driver = mapped_mod->cell(stringf("%s_lut", a_bit.wire->name.c_str())); + RTLIL::IdString driver_name; + if (GetSize(a_bit.wire) == 1) + driver_name = stringf("%s_lut", a_bit.wire->name.c_str()); + else + driver_name = stringf("%s[%d]_lut", a_bit.wire->name.c_str(), a_bit.offset); + RTLIL::Cell* driver = mapped_mod->cell(driver_name); log_assert(driver); auto driver_a = driver->getPort("\\A").chunks(); for (auto &chunk : driver_a) -- 2.30.2