From 6300156042c8ea54f146abe9a7deb9c7ebdef655 Mon Sep 17 00:00:00 2001 From: Uros Bizjak Date: Mon, 27 Sep 2010 08:25:55 +0200 Subject: [PATCH] i386.h (CLASS_MAX_NREGS): Also handle XCmode. * config/i386/i386.h (CLASS_MAX_NREGS): Also handle XCmode. (UNITS_PER_WORD): Define only when IN_LIBGCC2 is undefined. (MOVE_MAX_PIECES): Redefine using UNITS_PER_WORD. (ASM_OUTPUT_AVX_PREFIX): Simplify pointer addition. From-SVN: r164644 --- gcc/ChangeLog | 7 +++++++ gcc/config/i386/i386.c | 10 +++++----- gcc/config/i386/i386.h | 38 +++++++++++++++++--------------------- 3 files changed, 29 insertions(+), 26 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c80e26b9b1c..3128865f72f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2010-09-27 Uros Bizjak + + * config/i386/i386.h (CLASS_MAX_NREGS): Also handle XCmode. + (UNITS_PER_WORD): Define only when IN_LIBGCC2 is undefined. + (MOVE_MAX_PIECES): Redefine using UNITS_PER_WORD. + (ASM_OUTPUT_AVX_PREFIX): Simplify pointer addition. + 2010-09-26 Uros Bizjak * config/i386/i386.md (pro_epilogue_adjust_stack__add): Merge diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index af30e394067..627d8d20ea0 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -8777,11 +8777,9 @@ pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset, rtx insn; if (! TARGET_64BIT) - insn = emit_insn (gen_pro_epilogue_adjust_stack_si_add (dest, - src, offset)); + insn = gen_pro_epilogue_adjust_stack_si_add (dest, src, offset); else if (x86_64_immediate_operand (offset, DImode)) - insn = emit_insn (gen_pro_epilogue_adjust_stack_di_add (dest, - src, offset)); + insn = gen_pro_epilogue_adjust_stack_di_add (dest, src, offset); else { rtx tmp; @@ -8798,9 +8796,11 @@ pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset, insn = emit_insn (gen_rtx_SET (DImode, tmp, offset)); if (style < 0) RTX_FRAME_RELATED_P (insn) = 1; - insn = emit_insn (gen_pro_epilogue_adjust_stack_di_add (dest, src, tmp)); + + insn = gen_pro_epilogue_adjust_stack_di_add (dest, src, tmp); } + insn = emit_insn (insn); if (style >= 0) ix86_add_queued_cfa_restore_notes (insn); diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index f868f98f79b..b3439bc9f0c 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -674,9 +674,8 @@ enum target_cpu_default /* Width of a word, in units (bytes). */ #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) -#ifdef IN_LIBGCC2 -#define MIN_UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) -#else + +#ifndef IN_LIBGCC2 #define MIN_UNITS_PER_WORD 4 #endif @@ -863,8 +862,8 @@ enum target_cpu_default #define STACK_REGS #define IS_STACK_MODE(MODE) \ - (((MODE) == SFmode && (!TARGET_SSE || !TARGET_SSE_MATH)) \ - || ((MODE) == DFmode && (!TARGET_SSE2 || !TARGET_SSE_MATH)) \ + (((MODE) == SFmode && !(TARGET_SSE && TARGET_SSE_MATH)) \ + || ((MODE) == DFmode && !(TARGET_SSE2 && TARGET_SSE_MATH)) \ || (MODE) == XFmode) /* Cover class containing the stack registers. */ @@ -979,8 +978,7 @@ enum target_cpu_default Actually there are no two word move instructions for consecutive registers. And only registers 0-3 may have mov byte instructions - applied to them. - */ + applied to them. */ #define HARD_REGNO_NREGS(REGNO, MODE) \ (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ @@ -1187,7 +1185,8 @@ enum reg_class NON_Q_REGS, /* %esi %edi %ebp %esp */ INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ - GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/ + GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp + %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 */ FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ FLOAT_REGS, SSE_FIRST_REG, @@ -1416,10 +1415,13 @@ enum reg_class /* On the 80386, this is the size of MODE in words, except in the FP regs, where a single reg is always enough. */ #define CLASS_MAX_NREGS(CLASS, MODE) \ - (!MAYBE_INTEGER_CLASS_P (CLASS) \ - ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ - : (((((MODE) == XFmode ? 12 : GET_MODE_SIZE (MODE))) \ - + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) + (MAYBE_INTEGER_CLASS_P (CLASS) \ + ? ((MODE) == XFmode \ + ? (TARGET_64BIT ? 2 : 3) \ + : (MODE) == XCmode \ + ? (TARGET_64BIT ? 4 : 6) \ + : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) \ + : (COMPLEX_MODE_P (MODE) ? 2 : 1)) /* Return a class of registers that cannot change FROM mode to TO mode. */ @@ -1753,7 +1755,7 @@ typedef struct ix86_args { /* MOVE_MAX_PIECES is the number of bytes at a time which we can move efficiently, as opposed to MOVE_MAX which is the maximum number of bytes we can move with a single instruction. */ -#define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4) +#define MOVE_MAX_PIECES UNITS_PER_WORD /* If a memory-to-memory move would take MOVE_RATIO or more simple move-instruction pairs, we will do a movmem or libcall instead. @@ -1998,18 +2000,12 @@ do { \ #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ ix86_output_addr_diff_elt ((FILE), (VALUE), (REL)) -/* When we see %v, we will print the 'v' prefix if TARGET_AVX is - true. */ +/* When we see %v, we will print the 'v' prefix if TARGET_AVX is true. */ #define ASM_OUTPUT_AVX_PREFIX(STREAM, PTR) \ { \ if ((PTR)[0] == '%' && (PTR)[1] == 'v') \ - { \ - if (TARGET_AVX) \ - (PTR) += 1; \ - else \ - (PTR) += 2; \ - } \ + (PTR) += TARGET_AVX ? 1 : 2; \ } /* A C statement or statements which output an assembler instruction -- 2.30.2