From 6310051fc5c9d1b4df1b7bdaa354cc53059e316d Mon Sep 17 00:00:00 2001 From: Tong Shen Date: Mon, 25 Jan 2021 11:25:38 -0800 Subject: [PATCH] arch-x86: implement POPCNT instruction. Change-Id: Id6ddc1245c81a17720885f9038d55d0811ef7f4d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39615 Reviewed-by: Gabe Black Maintainer: Gabe Black Tested-by: kokoro --- src/arch/x86/decoder_tables.cc | 4 ++-- src/arch/x86/isa/decoder/two_byte_opcodes.isa | 3 +-- .../general_purpose/compare_and_test/bit_scan.py | 15 +++++++++++++++ src/arch/x86/isa/microops/regop.isa | 13 +++++++++++++ 4 files changed, 31 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/decoder_tables.cc b/src/arch/x86/decoder_tables.cc index 7ee5e0185..db749cf93 100644 --- a/src/arch/x86/decoder_tables.cc +++ b/src/arch/x86/decoder_tables.cc @@ -115,7 +115,7 @@ namespace X86ISA /* 8 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, /* 9 */ 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1, /* A */ 0 , 0 , 0 , 1 , 1 , 1 , 1 , 1 , 0 , 0 , 0 , 1 , 1 , 1 , 1 , 1, -/* B */ 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 0 , 0 , 1 , 1 , 1 , 1 , 1 , 1, +/* B */ 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 0 , 1 , 1 , 1 , 1 , 1 , 1, /* C */ 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0, /* D */ 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1, /* E */ 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1, @@ -234,7 +234,7 @@ namespace X86ISA /* 8 */ ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, /* 9 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , /* A */ 0 , 0 , 0 , 0 , BY, 0 , 0 , 0 , 0 , 0 , 0 , 0 , BY, 0 , 0 , 0 , -/* B */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , ZW, 0 , BY, 0 , 0 , 0 , 0 , 0 , +/* B */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , BY, 0 , 0 , 0 , 0 , 0 , /* C */ 0 , 0 , BY, 0 , BY, BY, BY, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , /* D */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , /* E */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa index f70e7bd1d..fe8a2bcdd 100644 --- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa @@ -754,8 +754,7 @@ } 0x17: decode OPCODE_OP_BOTTOM3 { 0x0: decode LEGACY_REP { - 0x0: WarnUnimpl::jmpe_Jz(); - 0x1: WarnUnimpl::popcnt_Gv_Ev(); + 0x1: POPCNT(Gv,Ev); } //0x1: group10_UD2(); 0x1: UD2(); diff --git a/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_scan.py b/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_scan.py index a755d2551..05bd3c4cf 100644 --- a/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_scan.py +++ b/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_scan.py @@ -350,4 +350,19 @@ def macroop BSF_R_P { end: fault "NoFault" }; + +def macroop POPCNT_R_R { + popcnt reg, regm, reg, dataSize=8 +}; + +def macroop POPCNT_R_M { + ld t1, seg, sib, disp + popcnt reg, t1, reg, dataSize=8 +}; + +def macroop POPCNT_R_P { + rdip t7 + ld t1, seg, riprel, disp + popcnt reg, t1, reg, dataSize=8 +}; ''' diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index c465dccd7..570c0847f 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -1764,4 +1764,17 @@ let {{ code = ''' DestReg = X86ISA::convX87TagsToXTags(FTW); ''' + + class Popcnt(RegOp): + code = ''' + DestReg = + merge(DestReg, __builtin_popcountl(psrc1), dataSize); + ''' + flag_code = ''' + ccFlagBits = ccFlagBits & ~(SFBit | AFBit | ZFBit | PFBit); + if (findZero(dataSize * 8, SrcReg1)) { + ccFlagBits = ccFlagBits | ZFBit; + } + cfofBits = cfofBits & ~(OFBit | CFBit); + ''' }}; -- 2.30.2