From 6318e3ce6df2484c4cc17856608e2a6354cd643a Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 26 Nov 2019 23:38:49 -0800
Subject: [PATCH] Fix wire width

---
 tests/various/submod.ys | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tests/various/submod.ys b/tests/various/submod.ys
index f50556d76..a0a3f2da5 100644
--- a/tests/various/submod.ys
+++ b/tests/various/submod.ys
@@ -1,8 +1,8 @@
 read_verilog <<EOT
-module top(input a, output [1:0] b);
+module top(input a, output b);
 wire c;
 (* submod="bar" *) sub s1(a, c);
-assign b[0] = c;
+assign b = c;
 endmodule
 
 module sub(input a, output c);
-- 
2.30.2