From 6319e0e3666cc7c71e651a29a96c77e2467ab06b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 13 Dec 2018 06:24:03 +0000 Subject: [PATCH] add rename description --- 3d_gpu/microarchitecture.mdwn | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/3d_gpu/microarchitecture.mdwn b/3d_gpu/microarchitecture.mdwn index 7975be84c..360970645 100644 --- a/3d_gpu/microarchitecture.mdwn +++ b/3d_gpu/microarchitecture.mdwn @@ -402,6 +402,21 @@ and there are several of them: ## Register Renaming +There are several potential well-known schemes for register-renaming: +*none of them will be used here*. The scheme below is a new form of +renaming that is a topologically and functionally **direct** equivalent +of the Tomasulo Algorithm with a Reorder Buffer, that came from the +"Register Alias Table" concept that is better suited to Scoreboards. +It works by flattening out Reservation Stations to one per FU (requiring +more FUs as a result). On top of this the function normally carried +out by "tags" of the RAT table may be merged-morphed into the role +carried out by the ROB Destination Register CAM which may be merged-morphed +into a single vector (per register) of 1-bit mutually-exclusive "CAMs" +that are added, very simply, to the FU-Register Dependency Matrix. + +In this way, exactly as in the Tomasulo Algorithm, there is absolutely no +need whatsoever for a separate PRF-ARF scheme. The PRF *is* the ARF. + Register-renaming will be done with a single extra mutually-exclusive bit in the FUxReg Dependency Matrix, which may be set on only one FU (per register). This bit indicates which of the FUs has the **most recent** destination -- 2.30.2