From 6323e73cc94627125a275b22b0b8ea290e750bc3 Mon Sep 17 00:00:00 2001 From: whitequark Date: Mon, 15 Apr 2019 14:29:46 +0000 Subject: [PATCH] README: fix some incorrect quoting. --- README.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index 4048ecbc7..d000c5d63 100644 --- a/README.md +++ b/README.md @@ -312,10 +312,10 @@ Verilog Attributes and non-standard features passes to identify input and output ports of cells. The Verilog backend also does not output blackbox modules on default. -- The ``dynports'' attribute is used by the Verilog front-end to mark modules +- The ``dynports`` attribute is used by the Verilog front-end to mark modules that have ports with a width that depends on a parameter. -- The ``hdlname'' attribute is used by some passes to document the original +- The ``hdlname`` attribute is used by some passes to document the original (HDL) name of a module when renaming a module. - The ``keep`` attribute on cells and wires is used to mark objects that should -- 2.30.2