From 63335f2b1916907bddbf0bad02360f6b9a4788d9 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 5 Sep 2020 16:32:23 +0100 Subject: [PATCH] increase wishbone address width to 29 for xics and gpio this may not be exactly correct, have to see how it goes --- src/soc/litex/florent/libresoc/core.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/litex/florent/libresoc/core.py b/src/soc/litex/florent/libresoc/core.py index d28d424d..23a363b9 100644 --- a/src/soc/litex/florent/libresoc/core.py +++ b/src/soc/litex/florent/libresoc/core.py @@ -61,9 +61,9 @@ class LibreSoC(CPU): self.data_width = 64 self.ibus = ibus = wishbone.Interface(data_width=64, adr_width=29) - self.xics_icp = icp = wishbone.Interface(data_width=32, adr_width=5) - self.xics_ics = ics = wishbone.Interface(data_width=32, adr_width=14) - self.simple_gpio = gpio = wishbone.Interface(data_width=32, adr_width=5) + self.xics_icp = icp = wishbone.Interface(data_width=32, adr_width=29) + self.xics_ics = ics = wishbone.Interface(data_width=32, adr_width=29) + self.simple_gpio = gpio = wishbone.Interface(data_width=32, adr_width=29) self.periph_buses = [ibus, dbus] self.memory_buses = [] -- 2.30.2