From 6345a94a9b134b1321b3b290bacde228b12af415 Mon Sep 17 00:00:00 2001 From: Jordan Justen Date: Wed, 28 May 2014 09:30:39 -0700 Subject: [PATCH] i965: Support array_layout == ALL_SLICES_AT_EACH_LOD for multiple LODs Previously array_layout ALL_SLICES_AT_EACH_LOD was only used for array spacing lod0 on gen7+ and therefore was only used with a single mip level. gen6 separate stencil & hiz only support LOD0, so we need to allocate the miptree similar to gen7+ array spacing lod0, except we also need space for multiple mip levels. (Since OpenGL stencil and depth support multiple LODs.) The miptree is allocated with tightly packed array slice spacing, but we still also pack the miplevels into the region similar to a normal multi mip level packing. A 2D Array texture with 2 slices and multiple LODs would look somewhat like this: +----------+ | | | | +----------+ | | | | +----------+ +---+ +-+ | | +-+ +---+ +-+ | | : +---+ v3: * Use new array_layout enum * ASCII art! Signed-off-by: Jordan Justen Reviewed-by: Topi Pohjolainen Acked-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_tex_layout.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c index 1ed62a6bcfa..d15f319158a 100644 --- a/src/mesa/drivers/dri/i965/brw_tex_layout.c +++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c @@ -203,6 +203,11 @@ brw_miptree_layout_2d(struct intel_mipmap_tree *mt) if (mt->compressed) img_height /= mt->align_h; + if (mt->array_layout == ALL_SLICES_AT_EACH_LOD) { + /* Compact arrays with separated miplevels */ + img_height *= depth; + } + /* Because the images are packed better, the final offset * might not be the maximal one: */ @@ -238,6 +243,7 @@ brw_miptree_layout_texture_array(struct brw_context *brw, struct intel_mipmap_tree *mt) { int h0, h1; + unsigned height = mt->physical_height0; h0 = ALIGN(mt->physical_height0, mt->align_h); h1 = ALIGN(minify(mt->physical_height0, 1), mt->align_h); @@ -251,11 +257,22 @@ brw_miptree_layout_texture_array(struct brw_context *brw, brw_miptree_layout_2d(mt); for (unsigned level = mt->first_level; level <= mt->last_level; level++) { + unsigned img_height; + img_height = ALIGN(height, mt->align_h); + if (mt->compressed) + img_height /= mt->align_h; + for (int q = 0; q < mt->physical_depth0; q++) { - intel_miptree_set_image_offset(mt, level, q, 0, q * physical_qpitch); + if (mt->array_layout == ALL_SLICES_AT_EACH_LOD) { + intel_miptree_set_image_offset(mt, level, q, 0, q * img_height); + } else { + intel_miptree_set_image_offset(mt, level, q, 0, q * physical_qpitch); + } } + height = minify(height, 1); } - mt->total_height = physical_qpitch * mt->physical_depth0; + if (mt->array_layout == ALL_LOD_IN_EACH_SLICE) + mt->total_height = physical_qpitch * mt->physical_depth0; align_cube(mt); } -- 2.30.2