From 63530e061b28e868f038c3a5515db50c3fb2b9c8 Mon Sep 17 00:00:00 2001
From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 28 Sep 2022 19:46:54 -0700
Subject: [PATCH] add bigint tests and fix madded pseudocode

---
 openpower/isa/svfixedarith.mdwn               |   2 +-
 .../decoder/isa/test_caller_bigint.py         |  22 +++
 src/openpower/test/bigint/__init__.py         |   0
 src/openpower/test/bigint/bigint_cases.py     | 145 ++++++++++++++++++
 4 files changed, 168 insertions(+), 1 deletion(-)
 create mode 100644 src/openpower/decoder/isa/test_caller_bigint.py
 create mode 100644 src/openpower/test/bigint/__init__.py
 create mode 100644 src/openpower/test/bigint/bigint_cases.py

diff --git a/openpower/isa/svfixedarith.mdwn b/openpower/isa/svfixedarith.mdwn
index 213ed2b9..18e70178 100644
--- a/openpower/isa/svfixedarith.mdwn
+++ b/openpower/isa/svfixedarith.mdwn
@@ -10,7 +10,7 @@ Pseudo-code:
     <!-- bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+MAXVL
     <!-- bit 8 of EXTRA is set  : RS.[s|v]=RC.[s|v]
     prod[0:127] <- (RA) * (RB)
-    sum[0:127] <- EXTZ(RC) + prod
+    sum[0:127] <- ([0] * 64 || (RC)) + prod
     RT <- sum[64:127]
     RS <- sum[0:63]
 
diff --git a/src/openpower/decoder/isa/test_caller_bigint.py b/src/openpower/decoder/isa/test_caller_bigint.py
new file mode 100644
index 00000000..55874819
--- /dev/null
+++ b/src/openpower/decoder/isa/test_caller_bigint.py
@@ -0,0 +1,22 @@
+""" bigint tests
+"""
+
+import unittest
+from openpower.test.runner import TestRunnerBase
+from openpower.test.bigint.bigint_cases import BigIntCases
+
+# writing the test_caller invocation this way makes it work with pytest
+
+
+class TestBigInt(TestRunnerBase):
+    def __init__(self, test):
+        assert test == 'test'
+        super().__init__(BigIntCases().test_data)
+
+    def test(self):
+        # dummy function to make unittest try to test this class
+        pass
+
+
+if __name__ == "__main__":
+    unittest.main()
diff --git a/src/openpower/test/bigint/__init__.py b/src/openpower/test/bigint/__init__.py
new file mode 100644
index 00000000..e69de29b
diff --git a/src/openpower/test/bigint/bigint_cases.py b/src/openpower/test/bigint/bigint_cases.py
new file mode 100644
index 00000000..b847ba09
--- /dev/null
+++ b/src/openpower/test/bigint/bigint_cases.py
@@ -0,0 +1,145 @@
+from openpower.test.common import TestAccumulatorBase, skip_case
+from openpower.sv.trans.svp64 import SVP64Asm
+from openpower.test.state import ExpectedState
+from openpower.simulator.program import Program
+
+_SHIFT_TEST_RANGE = range(-64, 128, 16)
+
+
+class BigIntCases(TestAccumulatorBase):
+    def case_madded(self):
+        lst = list(SVP64Asm(["madded 3,5,6,7"]))
+        gprs = [0] * 32
+        gprs[5] = 0x123456789ABCDEF
+        gprs[6] = 0xFEDCBA9876543210
+        gprs[7] = 0x02468ACE13579BDF
+        e = ExpectedState(pc=4, int_regs=gprs)
+        e.intregs[3] = (gprs[5] * gprs[6] + gprs[7]) % 2 ** 64
+        e.intregs[4] = (gprs[5] * gprs[6] + gprs[7]) >> 64
+        self.add_case(Program(lst, False), gprs, expected=e)
+
+    def case_divrem2du(self):
+        lst = list(SVP64Asm(["divrem2du 3,5,6,7"]))
+        gprs = [0] * 32
+        gprs[5] = 0x123456789ABCDEF
+        gprs[6] = 0xFEDCBA9876543210
+        gprs[7] = 0x02468ACE13579BDF
+        e = ExpectedState(pc=4, int_regs=gprs)
+        v = gprs[5] | (gprs[7] << 64)
+        e.intregs[3] = v // gprs[6]
+        e.intregs[4] = v % gprs[6]
+        self.add_case(Program(lst, False), gprs, expected=e)
+
+    # FIXME: test more divrem2du special cases
+
+    def case_dsld0(self):
+        prog = Program(list(SVP64Asm(["dsld 3,4,5,0"])), False)
+        for sh in _SHIFT_TEST_RANGE:
+            with self.subTest(sh=sh):
+                gprs = [0] * 32
+                gprs[3] = 0x123456789ABCDEF
+                gprs[4] = 0xFEDCBA9876543210
+                gprs[5] = sh % 2 ** 64
+                e = ExpectedState(pc=4, int_regs=gprs)
+                v = (gprs[3] << 64) | gprs[4]
+                v <<= sh % 64
+                e.intregs[3] = (v >> 64) % 2 ** 64
+                self.add_case(prog, gprs, expected=e)
+
+    def case_dsld1(self):
+        prog = Program(list(SVP64Asm(["dsld 3,4,5,1"])), False)
+        for sh in _SHIFT_TEST_RANGE:
+            with self.subTest(sh=sh):
+                gprs = [0] * 32
+                gprs[3] = 0x123456789ABCDEF
+                gprs[4] = 0xFEDCBA9876543210
+                gprs[5] = sh % 2 ** 64
+                e = ExpectedState(pc=4, int_regs=gprs)
+                v = (gprs[4] << 64) | gprs[3]
+                v <<= sh % 64
+                e.intregs[3] = (v >> 64) % 2 ** 64
+                self.add_case(prog, gprs, expected=e)
+
+    def case_dsld2(self):
+        prog = Program(list(SVP64Asm(["dsld 3,4,5,2"])), False)
+        for sh in _SHIFT_TEST_RANGE:
+            with self.subTest(sh=sh):
+                gprs = [0] * 32
+                gprs[3] = sh % 2 ** 64
+                gprs[4] = 0xFEDCBA9876543210
+                gprs[5] = 0x02468ACE13579BDF
+                e = ExpectedState(pc=4, int_regs=gprs)
+                v = (gprs[4] << 64) | gprs[5]
+                v <<= sh % 64
+                e.intregs[3] = (v >> 64) % 2 ** 64
+                self.add_case(prog, gprs, expected=e)
+
+    def case_dsld3(self):
+        prog = Program(list(SVP64Asm(["dsld 3,4,5,3"])), False)
+        for sh in _SHIFT_TEST_RANGE:
+            with self.subTest(sh=sh):
+                gprs = [0] * 32
+                gprs[3] = 0x123456789ABCDEF
+                gprs[4] = 0xFEDCBA9876543210
+                gprs[5] = sh % 2 ** 64
+                e = ExpectedState(pc=4, int_regs=gprs)
+                v = gprs[4]
+                v <<= sh % 64
+                e.intregs[3] = (v >> 64) % 2 ** 64
+                self.add_case(prog, gprs, expected=e)
+
+    def case_dsrd0(self):
+        prog = Program(list(SVP64Asm(["dsrd 3,4,5,0"])), False)
+        for sh in _SHIFT_TEST_RANGE:
+            with self.subTest(sh=sh):
+                gprs = [0] * 32
+                gprs[3] = 0x123456789ABCDEF
+                gprs[4] = 0xFEDCBA9876543210
+                gprs[5] = sh % 2 ** 64
+                e = ExpectedState(pc=4, int_regs=gprs)
+                v = (gprs[3] << 64) | gprs[4]
+                v >>= sh % 64
+                e.intregs[3] = v % 2 ** 64
+                self.add_case(prog, gprs, expected=e)
+
+    def case_dsrd1(self):
+        prog = Program(list(SVP64Asm(["dsrd 3,4,5,1"])), False)
+        for sh in _SHIFT_TEST_RANGE:
+            with self.subTest(sh=sh):
+                gprs = [0] * 32
+                gprs[3] = 0x123456789ABCDEF
+                gprs[4] = 0xFEDCBA9876543210
+                gprs[5] = sh % 2 ** 64
+                e = ExpectedState(pc=4, int_regs=gprs)
+                v = (gprs[4] << 64) | gprs[3]
+                v >>= sh % 64
+                e.intregs[3] = v % 2 ** 64
+                self.add_case(prog, gprs, expected=e)
+
+    def case_dsrd2(self):
+        prog = Program(list(SVP64Asm(["dsrd 3,4,5,2"])), False)
+        for sh in _SHIFT_TEST_RANGE:
+            with self.subTest(sh=sh):
+                gprs = [0] * 32
+                gprs[3] = sh % 2 ** 64
+                gprs[4] = 0xFEDCBA9876543210
+                gprs[5] = 0x02468ACE13579BDF
+                e = ExpectedState(pc=4, int_regs=gprs)
+                v = (gprs[4] << 64) | gprs[5]
+                v >>= sh % 64
+                e.intregs[3] = v % 2 ** 64
+                self.add_case(prog, gprs, expected=e)
+
+    def case_dsrd3(self):
+        prog = Program(list(SVP64Asm(["dsrd 3,4,5,3"])), False)
+        for sh in _SHIFT_TEST_RANGE:
+            with self.subTest(sh=sh):
+                gprs = [0] * 32
+                gprs[3] = 0x123456789ABCDEF
+                gprs[4] = 0xFEDCBA9876543210
+                gprs[5] = sh % 2 ** 64
+                e = ExpectedState(pc=4, int_regs=gprs)
+                v = gprs[4] << 64
+                v >>= sh % 64
+                e.intregs[3] = v % 2 ** 64
+                self.add_case(prog, gprs, expected=e)
-- 
2.30.2