From 635e66fec3addc5af7e2ab65793af7237e555922 Mon Sep 17 00:00:00 2001 From: Alan Lawrence Date: Tue, 15 Sep 2015 13:16:58 +0000 Subject: [PATCH] [AArch64 array_mode 8/8] Add d-registers to TARGET_ARRAY_MODE_SUPPORTED_P gcc/: * config/aarch64/aarch64.h (AARCH64_VALID_SIMD_DREG_MODE): New. * config/aarch64/aarch64.c (aarch64_array_mode_supported_p): Add AARCH64_VALID_SIMD_DREG_MODE. gcc/testsuite/: * gcc.target/aarch64/vect_int32x2x4_1.c: New. From-SVN: r227794 --- gcc/ChangeLog | 7 ++++++ gcc/config/aarch64/aarch64.c | 3 ++- gcc/config/aarch64/aarch64.h | 6 +++++ gcc/testsuite/ChangeLog | 4 ++++ .../gcc.target/aarch64/vect_int32x2x4_1.c | 22 +++++++++++++++++++ 5 files changed, 41 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/vect_int32x2x4_1.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a4911a0ff6a..38719b9e03a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2015-09-15 Alan Lawrence + + * config/aarch64/aarch64.h (AARCH64_VALID_SIMD_DREG_MODE): New. + + * config/aarch64/aarch64.c (aarch64_array_mode_supported_p): Add + AARCH64_VALID_SIMD_DREG_MODE. + 2015-09-15 Alan Lawrence * config/aarch64/aarch64-simd.md (aarch64_ld2r, diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 9c5cf4cb275..bbac271488f 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -677,7 +677,8 @@ aarch64_array_mode_supported_p (machine_mode mode, unsigned HOST_WIDE_INT nelems) { if (TARGET_SIMD - && AARCH64_VALID_SIMD_QREG_MODE (mode) + && (AARCH64_VALID_SIMD_QREG_MODE (mode) + || AARCH64_VALID_SIMD_DREG_MODE (mode)) && (nelems >= 2 && nelems <= 4)) return true; diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index 9669e014882..5a8db763222 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -872,6 +872,12 @@ extern enum aarch64_code_model aarch64_cmodel; (aarch64_cmodel == AARCH64_CMODEL_TINY \ || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC) +/* Modes valid for AdvSIMD D registers, i.e. that fit in half a Q register. */ +#define AARCH64_VALID_SIMD_DREG_MODE(MODE) \ + ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ + || (MODE) == V2SFmode || (MODE) == V4HFmode || (MODE) == DImode \ + || (MODE) == DFmode) + /* Modes valid for AdvSIMD Q registers. */ #define AARCH64_VALID_SIMD_QREG_MODE(MODE) \ ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 23558560441..6cea1084800 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2015-09-15 Alan Lawrence + + * gcc.target/aarch64/vect_int32x2x4_1.c: New. + 2015-09-15 Richard Biener PR middle-end/67563 diff --git a/gcc/testsuite/gcc.target/aarch64/vect_int32x2x4_1.c b/gcc/testsuite/gcc.target/aarch64/vect_int32x2x4_1.c new file mode 100644 index 00000000000..734cfd61bda --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vect_int32x2x4_1.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -fdump-rtl-expand" } */ + +#include + +uint32x2x4_t +test_1 (uint32x2x4_t a, uint32x2x4_t b) +{ + uint32x2x4_t result; + + for (unsigned index = 0; index < 4; ++index) + result.val[index] = a.val[index] + b.val[index]; + + return result; +} + +/* Should not use the stack in expand. */ +/* { dg-final { scan-rtl-dump-not "virtual-stack-vars" "expand" } } */ +/* Should not have to modify the stack pointer. */ +/* { dg-final { scan-assembler-not "\t(add|sub).*sp" } } */ +/* Should not have to store or load anything. */ +/* { dg-final { scan-assembler-not "\t(ld|st)\[rp\]" } } */ -- 2.30.2