From 63629fff9f1f54ed0d4bea05f22aee49b422d382 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 5 Sep 2022 11:26:35 +0100 Subject: [PATCH] add binary-compatibility column in comparison table --- openpower/sv/comparison_table.mdwn | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/openpower/sv/comparison_table.mdwn b/openpower/sv/comparison_table.mdwn index d48ae04cf..029638f50 100644 --- a/openpower/sv/comparison_table.mdwn +++ b/openpower/sv/comparison_table.mdwn @@ -1,19 +1,18 @@ **ISA Comparison Table to DRAFT SVP64** - discussion and research at -|ISA
name |No
opcodes|No
intrinsics|Taxonomy /
Class|setvl
scalable|Pred.
Masks|Twin
Pred|Vector
regs |128-bit
ops |Bigint |LDST
F/First|Data-dep
F-first|Pred-
Result|HW
Matrix|DCT/FFT
HW| -|---------------|--------------|-----------------|--------------------|-------------------|----------------|-------------|----------------|-----------------|--------|----------------|--------------------|----------------|-------------|--------------| -|SVP64 |5 [^1] |see [^2] |Scalable [^3] |yes |yes |yes [^4] |no [^5] |see [^6] |yes[^7] |yes [^8] |yes [^9] |yes [^10] |yes [^11] | yes[^12] | -|VSX |700+ |700?[^v1] |PackedSIMD |no |no |no |yes [^v2] |yes |no |no |no |no |yes [^v3] | no | -|NEON |~250 [^n1] |7088 [^n2] |PackedSIMD |no |no |no |yes |see [^b1] |no |no |no |no |no | no | -|SVE2 |~1000 [^e1] |6040 [^e2] |Predicated SIMD[^e3]|no [^e3] |yes |no |yes |see [^b1] |no |yes [^8] |no |no |yes [^e4] | no | -|AVX512 [^x1] |~1000s [^x2] |7256 [^x3] |Predicated SIMD |no |yes |no |yes |see [^b1] |no |no |no |no |yes [^x4] | no | -|RVV [^r1] |~190 [^r2] |~25000[^r3] |Scalable[^r4] |yes |yes |no |yes |yes [^r5] |no |yes |no |no |no | no | -|Aurora SX[^s1] |~200 [^s2] |unknown [^s3] |Scalable [^s4] |yes |yes |no |yes |no |no |no |no |no |? | no | -|66000[^m1] |~200 |unknown |AutoVec[^m1] |see [^m1] |see[^m1] |no |see [^m1] |no |yes[^m2]|see [^m1] |no |no |no | no | +|ISA
name |No
opcodes|No
intrinsics|Taxonomy /
Class|Binary
Compat|setvl
scalable|Pred.
Masks|Twin
Pred|Vector
regs |128-bit
ops |Big
int|LDST
F/First|Data-dep
F-first|Pred
Result|HW
Matrix|DCT
FFT | +|---------------|--------------|-----------------|--------------------|------------------|-------------------|----------------|-------------|----------------|-----------------|------------|----------------|--------------------|----------------|-------------|--------------| +|SVP64 |6 [^1] |see [^2] |Scalable [^3] |yes |yes |yes |yes [^4] |no [^5] |see [^6] |yes[^7] |yes [^8] |yes [^9] |yes [^10] |yes [^11] | yes[^12] | +|VSX |700+ |700?[^v1] |PackedSIMD |yes |no |no |no |yes [^v2] |yes |no |no |no |no |yes [^v3] | no | +|NEON |~250[^n1] |7088 [^n2] |PackedSIMD |yes |no |no |no |yes |see [^b1] |no |no |no |no |no | no | +|SVE2 |~1000[^e1] |6040 [^e2] |PredSIMD[^e3] |NO [^nc] |no [^e3] |yes |no |yes |see [^b1] |no |yes [^8] |no |no |yes [^e4] | no | +|AVX512[^x1] |~1000s[^x2] |7256[^x3] |PredSIMD |yes |no |yes |no |yes |see[^b1] |no |no |no |no |yes[^x4] | no | +|RVV [^r1] |~190[^r2] |~25000[^r3] |Scalable[^r4] |NO [^nc] |yes |yes |no |yes |yes [^r5] |no |yes |no |no |no | no | +|AuroraSX[^s1] |~200[^s2] |unknown[^s3] |Scalable[^s4] |yes |yes |yes |no |yes |no |no |no |no |no |? | no | +|66000[^m1] |~200 |unknown |AutoVec[^m1] |yes |see [^m1] |see[^m1] |no |see [^m1] |no |yes[^m2] |see [^m1] |no |no |no | no | [^1]: plus EXT001 24-bit prefixing using 25% of EXT001 space. See [[sv/svp64]] -[^2]: If treated as a 1-Dimensional ISA, and designed badly, the 24-bit Prefix expands 200+ scalar instructions to well over a million intrinsics (N~=10^4 **times** M~=10^2). - If treated as a 2-Dimensional ISA and designed well, there are far less. N prefix intrinsics **plus** M scalar instruction intrinsics, where N is likely to be of the order of 10^2 and M of the order of 10^2. +[^2]: If treated as a 1-Dimensional ISA, and designed badly, the 24-bit Prefix expands 200+ scalar instructions to well over a million intrinsics (N~=10^4 **times** M~=10^2). If treated as a 2-Dimensional ISA and designed well, there are far less. N prefix intrinsics **plus** M scalar instruction intrinsics, where N is likely to be of the order of 10^2 and M of the order of 10^2. [^3]: A 2-Dimensional Scalable Vector ISA **specifically designed for the Power ISA** with both Horizontal-First and Vertical-First Modes. See [[sv/vector_isa_comparison]] [^4]: on specific operations. See [[opcode_regs_deduped]] for full list. Key: 2P - Twin Predication, 1P - Single-Predicate [^5]: SVP64 provides a Vector concept on top of the **Scalar** GPR, FPR and CR Fields, extended to 128 entries. @@ -54,3 +53,4 @@ [^b1]: Although registers may be 128-bit in NEON, SVE2, and AVX, unlike VSX there are very few (or no) actual arithmetic 128-bit operations. Only RVV and SVP64 have the possibility of 128-bit ops [^m1]: Mitch Alsup's MyISA 66000 is available on request. A powerful RISC ISA with a **Hardware-level auto-vectorisation** LOOP built-in as an extension named VVM. Classified as "Vertical-First". [^m2]: MyISA 66000 has a CARRY register up to 64-bit. Repeated application of FMA (esp. within Auto-Vectored LOOPS) automatically and inherently creates big-int operations with zero effort. +[^nc]: "Silicon-Partner" Scaling achieved through allowing same instruction to act on different regfile size and bitwidth. This catastrophically results in binary non-interoperability. -- 2.30.2