From 63632b1d359860be78f84e0642d700a82f39033f Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 20 Oct 2018 02:13:28 +0100 Subject: [PATCH] make sv_regbase_t public --- riscv/sv_insn_redirect.cc | 1 + riscv/sv_reg.h | 6 +++--- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc index 6dbf7e0..92f93a5 100644 --- a/riscv/sv_insn_redirect.cc +++ b/riscv/sv_insn_redirect.cc @@ -268,6 +268,7 @@ sv_reg_t::operator sv_reg_t () sv_reg_t sv_proc_t::rv_add(sv_reg_t const & lhs, sv_reg_t const & rhs) { + uint8_t elwidth = lhs.get_width(rhs); return lhs + rhs; } diff --git a/riscv/sv_reg.h b/riscv/sv_reg.h index f704f35..7138780 100644 --- a/riscv/sv_reg.h +++ b/riscv/sv_reg.h @@ -14,7 +14,7 @@ public: uint8_t elwidth; public: uint8_t get_width() const { return elwidth; } - uint8_t get_width(sv_regbase_t const&r) { + uint8_t get_width(sv_regbase_t const&r) const { // bitfield 0b00=default, 0b01=default/2, 0b10=default*2, 0b11=8-bit uint8_t tb[16] = { 0x0, // default-default: default 0x0, // default-default/2: default @@ -37,7 +37,7 @@ public: } }; -class sv_reg_t : sv_regbase_t { +class sv_reg_t : public sv_regbase_t { public: sv_reg_t(uint64_t _reg) : sv_regbase_t(), reg(_reg) { } // default elwidth sv_reg_t(uint64_t _reg, uint8_t _elwidth) : sv_regbase_t(_elwidth), reg(_reg) @@ -50,7 +50,7 @@ public: operator sv_sreg_t() const&; }; -class sv_sreg_t : sv_regbase_t { +class sv_sreg_t : public sv_regbase_t { public: sv_sreg_t(int64_t _reg) : sv_regbase_t(), reg(_reg) {} // default elwidth sv_sreg_t(int64_t _reg, uint8_t _elwidth) : sv_regbase_t(_elwidth), -- 2.30.2