From 636a9a890073af7540e9dc1e96ec180dcb42e50e Mon Sep 17 00:00:00 2001 From: Jeff Law Date: Sat, 19 Nov 2016 10:52:04 -0700 Subject: [PATCH] re PR target/25111 ([m68k] bset is not used for A = 1 << (B & 31) on ColdFire) PR target/25111 * config/m68k/m68k.md (bsetdreg): New pattern. (bchgdreg, bclrdreg): Likewise. PR target/25111 * gcc.target/m68k/pr25111.c: New test. From-SVN: r242623 --- gcc/ChangeLog | 6 ++++ gcc/config/m68k/m68k.md | 39 +++++++++++++++++++++++++ gcc/testsuite/ChangeLog | 5 ++++ gcc/testsuite/gcc.target/m68k/pr25111.c | 32 ++++++++++++++++++++ 4 files changed, 82 insertions(+) create mode 100644 gcc/testsuite/gcc.target/m68k/pr25111.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index fd09a790494..1d560f5c68e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2016-11-19 Jeff Law + + PR target/25111 + * config/m68k/m68k.md (bsetdreg): New pattern. + (bchgdreg, bclrdreg): Likewise. + 2016-11-19 Kaz Kojima PR target/78426 diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md index 7b7f3731f07..208561996e7 100644 --- a/gcc/config/m68k/m68k.md +++ b/gcc/config/m68k/m68k.md @@ -5336,6 +5336,45 @@ } [(set_attr "type" "bitrw")]) +(define_insn "*bsetdreg" + [(set (match_operand:SI 0 "register_operand" "+d") + (ior:SI (ashift:SI (const_int 1) + (and:SI (match_operand:SI 1 "register_operand" "d") + (const_int 31))) + (match_operand:SI 2 "register_operand" "0")))] + "" +{ + CC_STATUS_INIT; + return "bset %1,%0"; +} + [(set_attr "type" "bitrw")]) + +(define_insn "*bchgdreg" + [(set (match_operand:SI 0 "register_operand" "+d") + (xor:SI (ashift:SI (const_int 1) + (and:SI (match_operand:SI 1 "register_operand" "d") + (const_int 31))) + (match_operand:SI 2 "register_operand" "0")))] + "" +{ + CC_STATUS_INIT; + return "bchg %1,%0"; +} + [(set_attr "type" "bitrw")]) + +(define_insn "*bclrdreg" + [(set (match_operand:SI 0 "register_operand" "+d") + (and:SI (rotate:SI (const_int -2) + (and:SI (match_operand:SI 1 "register_operand" "d") + (const_int 31))) + (match_operand:SI 2 "register_operand" "0")))] + "" +{ + CC_STATUS_INIT; + return "bclr %1,%0"; +} + [(set_attr "type" "bitrw")]) + ;; clear bit, bit number is int (define_insn "bclrmemqi" [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m") diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 50b8888ab4b..41133d82280 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2016-11-18 Jeff Law + + PR target/25111 + * gcc.target/m68k/pr25111.c: New test. + 2016-11-18 Jakub Jelinek PR c++/68180 diff --git a/gcc/testsuite/gcc.target/m68k/pr25111.c b/gcc/testsuite/gcc.target/m68k/pr25111.c new file mode 100644 index 00000000000..950eedaff3d --- /dev/null +++ b/gcc/testsuite/gcc.target/m68k/pr25111.c @@ -0,0 +1,32 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +/* { dg-final { scan-assembler-times "bset" 1 } } */ +/* { dg-final { scan-assembler-times "bchg" 1 } } */ +/* { dg-final { scan-assembler-times "bclr" 1 } } */ + +int bar (void); + +int +foo1 (int b) +{ + int a = bar (); + return ( a | (1 << (b & 31))); +} + +int +foo2 (int b) +{ + int a = bar (); + return ( a ^ (1 << (b & 31))); +} + + +int +foo3 (int b) +{ + int a = bar (); + return ( a & ~(1 << (b & 31))); +} + + -- 2.30.2