From 637f45f3909326d18d6f64ff04eeb3bef205d2f8 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Daniel=20Sch=C3=BCrmann?= Date: Tue, 7 Apr 2020 10:24:36 +0100 Subject: [PATCH] aco: setup subdword regclasses for ssa_undef & load_const Reviewed-by: Rhys Perry Part-of: --- .../aco_instruction_selection_setup.cpp | 20 ++++++++----------- 1 file changed, 8 insertions(+), 12 deletions(-) diff --git a/src/amd/compiler/aco_instruction_selection_setup.cpp b/src/amd/compiler/aco_instruction_selection_setup.cpp index dd64b79331d..dba3bf075f1 100644 --- a/src/amd/compiler/aco_instruction_selection_setup.cpp +++ b/src/amd/compiler/aco_instruction_selection_setup.cpp @@ -361,12 +361,10 @@ void init_context(isel_context *ctx, nir_shader *shader) break; } case nir_instr_type_load_const: { - unsigned size = nir_instr_as_load_const(instr)->def.num_components; - if (nir_instr_as_load_const(instr)->def.bit_size == 64) - size *= 2; - else if (nir_instr_as_load_const(instr)->def.bit_size == 1) - size *= lane_mask_size; - allocated[nir_instr_as_load_const(instr)->def.index] = Temp(0, RegClass(RegType::sgpr, size)); + unsigned num_components = nir_instr_as_load_const(instr)->def.num_components; + unsigned bit_size = nir_instr_as_load_const(instr)->def.bit_size; + RegClass rc = get_reg_class(ctx, RegType::sgpr, num_components, bit_size); + allocated[nir_instr_as_load_const(instr)->def.index] = Temp(0, rc); break; } case nir_instr_type_intrinsic: { @@ -552,12 +550,10 @@ void init_context(isel_context *ctx, nir_shader *shader) break; } case nir_instr_type_ssa_undef: { - unsigned size = nir_instr_as_ssa_undef(instr)->def.num_components; - if (nir_instr_as_ssa_undef(instr)->def.bit_size == 64) - size *= 2; - else if (nir_instr_as_ssa_undef(instr)->def.bit_size == 1) - size *= lane_mask_size; - allocated[nir_instr_as_ssa_undef(instr)->def.index] = Temp(0, RegClass(RegType::sgpr, size)); + unsigned num_components = nir_instr_as_ssa_undef(instr)->def.num_components; + unsigned bit_size = nir_instr_as_ssa_undef(instr)->def.bit_size; + RegClass rc = get_reg_class(ctx, RegType::sgpr, num_components, bit_size); + allocated[nir_instr_as_ssa_undef(instr)->def.index] = Temp(0, rc); break; } case nir_instr_type_phi: { -- 2.30.2