From 639af2a7c637e39b2d30f9891f67da76af50cab7 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Tue, 15 Nov 2016 00:07:35 -0800 Subject: [PATCH] intel: Convert devinfo->urb.min_*_entries into an array. Signed-off-by: Kenneth Graunke Reviewed-by: Topi Pohjolainen --- src/intel/common/gen_device_info.c | 86 +++++++++++++++++++--------- src/intel/common/gen_device_info.h | 7 ++- src/intel/vulkan/genX_pipeline.c | 6 +- src/mesa/drivers/dri/i965/gen6_urb.c | 3 +- src/mesa/drivers/dri/i965/gen7_urb.c | 9 +-- 5 files changed, 73 insertions(+), 38 deletions(-) diff --git a/src/intel/common/gen_device_info.c b/src/intel/common/gen_device_info.c index bf5f05dc18a..42677516088 100644 --- a/src/intel/common/gen_device_info.c +++ b/src/intel/common/gen_device_info.c @@ -81,7 +81,9 @@ static const struct gen_device_info gen_device_info_snb_gt1 = { .max_wm_threads = 40, .urb = { .size = 32, - .min_vs_entries = 24, + .min_entries = { + [MESA_SHADER_VERTEX] = 24, + }, .max_entries = { [MESA_SHADER_VERTEX] = 256, [MESA_SHADER_GEOMETRY] = 256, @@ -103,7 +105,9 @@ static const struct gen_device_info gen_device_info_snb_gt2 = { .max_wm_threads = 80, .urb = { .size = 64, - .min_vs_entries = 24, + .min_entries = { + [MESA_SHADER_VERTEX] = 24, + }, .max_entries = { [MESA_SHADER_VERTEX] = 256, [MESA_SHADER_GEOMETRY] = 256, @@ -130,8 +134,10 @@ static const struct gen_device_info gen_device_info_ivb_gt1 = { .max_cs_threads = 36, .urb = { .size = 128, - .min_vs_entries = 32, - .min_ds_entries = 10, + .min_entries = { + [MESA_SHADER_VERTEX] = 32, + [MESA_SHADER_TESS_EVAL] = 10, + }, .max_entries = { [MESA_SHADER_VERTEX] = 512, [MESA_SHADER_TESS_CTRL] = 32, @@ -152,8 +158,10 @@ static const struct gen_device_info gen_device_info_ivb_gt2 = { .max_cs_threads = 64, .urb = { .size = 256, - .min_vs_entries = 32, - .min_ds_entries = 10, + .min_entries = { + [MESA_SHADER_VERTEX] = 32, + [MESA_SHADER_TESS_EVAL] = 10, + }, .max_entries = { [MESA_SHADER_VERTEX] = 704, [MESA_SHADER_TESS_CTRL] = 64, @@ -175,8 +183,10 @@ static const struct gen_device_info gen_device_info_byt = { .max_cs_threads = 32, .urb = { .size = 128, - .min_vs_entries = 32, - .min_ds_entries = 10, + .min_entries = { + [MESA_SHADER_VERTEX] = 32, + [MESA_SHADER_TESS_EVAL] = 10, + }, .max_entries = { [MESA_SHADER_VERTEX] = 512, [MESA_SHADER_TESS_CTRL] = 32, @@ -203,8 +213,10 @@ static const struct gen_device_info gen_device_info_hsw_gt1 = { .max_cs_threads = 70, .urb = { .size = 128, - .min_vs_entries = 32, - .min_ds_entries = 10, + .min_entries = { + [MESA_SHADER_VERTEX] = 32, + [MESA_SHADER_TESS_EVAL] = 10, + }, .max_entries = { [MESA_SHADER_VERTEX] = 640, [MESA_SHADER_TESS_CTRL] = 64, @@ -225,8 +237,10 @@ static const struct gen_device_info gen_device_info_hsw_gt2 = { .max_cs_threads = 70, .urb = { .size = 256, - .min_vs_entries = 64, - .min_ds_entries = 10, + .min_entries = { + [MESA_SHADER_VERTEX] = 64, + [MESA_SHADER_TESS_EVAL] = 10, + }, .max_entries = { [MESA_SHADER_VERTEX] = 1664, [MESA_SHADER_TESS_CTRL] = 128, @@ -247,8 +261,10 @@ static const struct gen_device_info gen_device_info_hsw_gt3 = { .max_cs_threads = 70, .urb = { .size = 512, - .min_vs_entries = 64, - .min_ds_entries = 10, + .min_entries = { + [MESA_SHADER_VERTEX] = 64, + [MESA_SHADER_TESS_EVAL] = 10, + }, .max_entries = { [MESA_SHADER_VERTEX] = 1664, [MESA_SHADER_TESS_CTRL] = 128, @@ -279,8 +295,10 @@ static const struct gen_device_info gen_device_info_bdw_gt1 = { .max_cs_threads = 42, .urb = { .size = 192, - .min_vs_entries = 64, - .min_ds_entries = 34, + .min_entries = { + [MESA_SHADER_VERTEX] = 64, + [MESA_SHADER_TESS_EVAL] = 34, + }, .max_entries = { [MESA_SHADER_VERTEX] = 2560, [MESA_SHADER_TESS_CTRL] = 504, @@ -296,8 +314,10 @@ static const struct gen_device_info gen_device_info_bdw_gt2 = { .max_cs_threads = 56, .urb = { .size = 384, - .min_vs_entries = 64, - .min_ds_entries = 34, + .min_entries = { + [MESA_SHADER_VERTEX] = 64, + [MESA_SHADER_TESS_EVAL] = 34, + }, .max_entries = { [MESA_SHADER_VERTEX] = 2560, [MESA_SHADER_TESS_CTRL] = 504, @@ -313,8 +333,10 @@ static const struct gen_device_info gen_device_info_bdw_gt3 = { .max_cs_threads = 56, .urb = { .size = 384, - .min_vs_entries = 64, - .min_ds_entries = 34, + .min_entries = { + [MESA_SHADER_VERTEX] = 64, + [MESA_SHADER_TESS_EVAL] = 34, + }, .max_entries = { [MESA_SHADER_VERTEX] = 2560, [MESA_SHADER_TESS_CTRL] = 504, @@ -336,8 +358,10 @@ static const struct gen_device_info gen_device_info_chv = { .max_cs_threads = 6 * 7, .urb = { .size = 192, - .min_vs_entries = 34, - .min_ds_entries = 34, + .min_entries = { + [MESA_SHADER_VERTEX] = 34, + [MESA_SHADER_TESS_EVAL] = 34, + }, .max_entries = { [MESA_SHADER_VERTEX] = 640, [MESA_SHADER_TESS_CTRL] = 80, @@ -363,8 +387,10 @@ static const struct gen_device_info gen_device_info_chv = { .max_cs_threads = 56, \ .urb = { \ .size = 384, \ - .min_vs_entries = 64, \ - .min_ds_entries = 34, \ + .min_entries = { \ + [MESA_SHADER_VERTEX] = 64, \ + [MESA_SHADER_TESS_EVAL] = 34, \ + }, \ .max_entries = { \ [MESA_SHADER_VERTEX] = 1856, \ [MESA_SHADER_TESS_CTRL] = 672, \ @@ -386,8 +412,10 @@ static const struct gen_device_info gen_device_info_chv = { .max_cs_threads = 6 * 6, \ .urb = { \ .size = 192, \ - .min_vs_entries = 34, \ - .min_ds_entries = 34, \ + .min_entries = { \ + [MESA_SHADER_VERTEX] = 34, \ + [MESA_SHADER_TESS_EVAL] = 34, \ + }, \ .max_entries = { \ [MESA_SHADER_VERTEX] = 704, \ [MESA_SHADER_TESS_CTRL] = 256, \ @@ -405,8 +433,10 @@ static const struct gen_device_info gen_device_info_chv = { .max_cs_threads = 6 * 6, \ .urb = { \ .size = 128, \ - .min_vs_entries = 34, \ - .min_ds_entries = 34, \ + .min_entries = { \ + [MESA_SHADER_VERTEX] = 34, \ + [MESA_SHADER_TESS_EVAL] = 34, \ + }, \ .max_entries = { \ [MESA_SHADER_VERTEX] = 352, \ [MESA_SHADER_TESS_CTRL] = 128, \ diff --git a/src/intel/common/gen_device_info.h b/src/intel/common/gen_device_info.h index 445addc0838..2c4faf4d0d1 100644 --- a/src/intel/common/gen_device_info.h +++ b/src/intel/common/gen_device_info.h @@ -135,8 +135,11 @@ struct gen_device_info * urb.size = URB Size (kbytes) / slice count */ unsigned size; - unsigned min_vs_entries; - unsigned min_ds_entries; + + /** + * The minimum number of URB entries. See the 3DSTATE_URB_ docs. + */ + unsigned min_entries[4]; /** * The maximum number of URB entries. See the 3DSTATE_URB_ docs. diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c index 7e263f826bf..89c9caf9fea 100644 --- a/src/intel/vulkan/genX_pipeline.c +++ b/src/intel/vulkan/genX_pipeline.c @@ -234,8 +234,8 @@ genX(emit_urb_setup)(struct anv_device *device, struct anv_batch *batch, /* VS has a lower limit on the number of URB entries */ unsigned vs_chunks = - ALIGN(device->info.urb.min_vs_entries * vs_entry_size_bytes, - chunk_size_bytes) / chunk_size_bytes; + ALIGN(device->info.urb.min_entries[MESA_SHADER_VERTEX] * + vs_entry_size_bytes, chunk_size_bytes) / chunk_size_bytes; unsigned vs_wants = ALIGN(device->info.urb.max_entries[MESA_SHADER_VERTEX] * vs_entry_size_bytes, @@ -303,7 +303,7 @@ genX(emit_urb_setup)(struct anv_device *device, struct anv_batch *batch, /* Finally, sanity check to make sure we have at least the minimum number * of entries needed for each stage. */ - assert(nr_vs_entries >= device->info.urb.min_vs_entries); + assert(nr_vs_entries >= device->info.urb.min_entries[MESA_SHADER_VERTEX]); if (active_stages & VK_SHADER_STAGE_GEOMETRY_BIT) assert(nr_gs_entries >= 2); diff --git a/src/mesa/drivers/dri/i965/gen6_urb.c b/src/mesa/drivers/dri/i965/gen6_urb.c index b91d7fa3ab3..e69a1dfada1 100644 --- a/src/mesa/drivers/dri/i965/gen6_urb.c +++ b/src/mesa/drivers/dri/i965/gen6_urb.c @@ -74,7 +74,8 @@ gen6_upload_urb(struct brw_context *brw, unsigned vs_size, brw->urb.nr_vs_entries = ROUND_DOWN_TO(nr_vs_entries, 4); brw->urb.nr_gs_entries = ROUND_DOWN_TO(nr_gs_entries, 4); - assert(brw->urb.nr_vs_entries >= devinfo->urb.min_vs_entries); + assert(brw->urb.nr_vs_entries >= + devinfo->urb.min_entries[MESA_SHADER_VERTEX]); assert(brw->urb.nr_vs_entries % 4 == 0); assert(brw->urb.nr_gs_entries % 4 == 0); assert(vs_size <= 5); diff --git a/src/mesa/drivers/dri/i965/gen7_urb.c b/src/mesa/drivers/dri/i965/gen7_urb.c index ca347b49d72..eb811b45659 100644 --- a/src/mesa/drivers/dri/i965/gen7_urb.c +++ b/src/mesa/drivers/dri/i965/gen7_urb.c @@ -284,7 +284,8 @@ gen7_upload_urb(struct brw_context *brw, unsigned vs_size, * greater than or equal to 192." */ unsigned vs_min_entries = - tess_present && brw->gen == 8 ? 192 : devinfo->urb.min_vs_entries; + tess_present && brw->gen == 8 ? + 192 : devinfo->urb.min_entries[MESA_SHADER_VERTEX]; /* Min VS Entries isn't a multiple of 8 on Cherryview/Broxton; round up */ vs_min_entries = ALIGN(vs_min_entries, vs_granularity); @@ -327,8 +328,8 @@ gen7_upload_urb(struct brw_context *brw, unsigned vs_size, hs_entry_size_bytes, chunk_size_bytes) - hs_chunks; ds_chunks = - DIV_ROUND_UP(devinfo->urb.min_ds_entries * ds_entry_size_bytes, - chunk_size_bytes); + DIV_ROUND_UP(devinfo->urb.min_entries[MESA_SHADER_TESS_EVAL] * + ds_entry_size_bytes, chunk_size_bytes); ds_wants = DIV_ROUND_UP(devinfo->urb.max_entries[MESA_SHADER_TESS_EVAL] * ds_entry_size_bytes, chunk_size_bytes) - ds_chunks; @@ -410,7 +411,7 @@ gen7_upload_urb(struct brw_context *brw, unsigned vs_size, assert(nr_gs_entries >= 2); if (tess_present) { assert(nr_hs_entries >= 1); - assert(nr_ds_entries >= devinfo->urb.min_ds_entries); + assert(nr_ds_entries >= devinfo->urb.min_entries[MESA_SHADER_TESS_EVAL]); } /* Gen7 doesn't actually use brw->urb.nr_{vs,gs}_entries, but it seems -- 2.30.2