From 63a813af9c53895c9e08e71d132d4bb435ccf8c2 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 30 Sep 2019 08:26:38 +0200 Subject: [PATCH] soc_core: fix cpu_type=None case and add test for it --- litex/soc/cores/cpu/__init__.py | 4 ++++ litex/soc/integration/soc_core.py | 2 ++ test/test_targets.py | 5 +++++ 3 files changed, 11 insertions(+) diff --git a/litex/soc/cores/cpu/__init__.py b/litex/soc/cores/cpu/__init__.py index ec57b0b2..b8d6aad2 100644 --- a/litex/soc/cores/cpu/__init__.py +++ b/litex/soc/cores/cpu/__init__.py @@ -18,6 +18,10 @@ class CPU(Module): interrupts = {} mem_map = {} +class CPUNone(CPU): + data_width = 32 + reset_address = 0x00000000 + # CPUS --------------------------------------------------------------------------------------------- from litex.soc.cores.cpu.lm32 import LM32 diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 85c6403c..b3f1ae40 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -193,6 +193,8 @@ class SoCCore(Module): # Allow SoCController to reset the CPU if with_ctrl: self.comb += self.cpu.reset.eq(self.ctrl.reset) + else: + self.add_cpu(cpu.CPUNone()) # Add user's interrupts (needs to be done after CPU interrupts are allocated) for _name, _id in self.interrupt_map.items(): diff --git a/test/test_targets.py b/test/test_targets.py index 157481e7..038faedb 100644 --- a/test/test_targets.py +++ b/test/test_targets.py @@ -121,6 +121,11 @@ litex/boards/targets/simple.py litex.boards.platforms.{p} \ """.format(p=p) subprocess.check_call(cmd, shell=True) + def test_cpu_none(self): + from litex.boards.targets.arty import BaseSoC + errors = build_test([BaseSoC(cpu_type=None)]) + self.assertEqual(errors, 0) + def run_variants(self, cpu, variants): for v in variants: with self.subTest(cpu=cpu, variant=v): -- 2.30.2