From 63a990ea0741f17c98bfddb75464806e7c78b52d Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 29 Jul 2021 15:40:22 +0100 Subject: [PATCH] --- nlnet_2021_lip6_vlsi.mdwn | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/nlnet_2021_lip6_vlsi.mdwn b/nlnet_2021_lip6_vlsi.mdwn index 05ee74591..200374f0b 100644 --- a/nlnet_2021_lip6_vlsi.mdwn +++ b/nlnet_2021_lip6_vlsi.mdwn @@ -26,7 +26,7 @@ engendered and fostered where at present NDAs rife through the VLSI Industry prevent and prohibit discussion and general improvements beneficial to users. -The expected outcome is to improve Coriolis2, HITAS/TAGLE and extend the +The expected outcome is to improve Coriolis2, HITAS/YAGLE and extend the whole toolchain so that it is faster, able to handle larger ASIC designs, and can perform Logical Validation. Also to be improved and tested is support for lower geometries (starting with 130nm) @@ -47,7 +47,7 @@ EUR $50,000. To improve the speed of the GUI front-end, to make it possible to handle larger ASIC designs, to add LVS capability, improve the internal data format (to better handle mixed case module and signal names), integrate -the Static Timing Analysis tool (HITAS, TAGLE), to complete the conversion +the Static Timing Analysis tool (HITAS) and YAGLE gate-level extraction tool, to complete the conversion to python 3, to try smaller geometry ASICs (beginning with 130nm), and potentially investigate using multi-processing to speed up completion. -- 2.30.2