From 63e497cbe41f512f28f7f11aa29f83cf4bb27015 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 13 Nov 2020 15:45:51 +0000 Subject: [PATCH] remove io_in/out now it is not needed for niolib --- src/soc/litex/florent/libresoc/core.py | 7 ------- src/soc/litex/florent/ls180soc.py | 8 -------- 2 files changed, 15 deletions(-) diff --git a/src/soc/litex/florent/libresoc/core.py b/src/soc/litex/florent/libresoc/core.py index 728034de..370f9cdc 100644 --- a/src/soc/litex/florent/libresoc/core.py +++ b/src/soc/litex/florent/libresoc/core.py @@ -157,10 +157,6 @@ class LibreSoC(CPU): self.platform = platform self.variant = variant self.reset = Signal() - # used by coriolis2 to connect up IO VSS/VDD to niolib GPIO cell lib - if False: - self.io_in = Signal() - self.io_out = Signal() irq_en = "noirq" not in variant @@ -216,9 +212,6 @@ class LibreSoC(CPU): o_busy_o = Signal(), # not connected o_memerr_o = Signal(), # not connected o_pc_o = Signal(64), # not connected - - #o_io_in = 0, # set io_in signal to False (for niolib) - #o_io_out = 1, # set io_in signal to True (for niolib) ) if irq_en: diff --git a/src/soc/litex/florent/ls180soc.py b/src/soc/litex/florent/ls180soc.py index 93ed3890..4279effc 100755 --- a/src/soc/litex/florent/ls180soc.py +++ b/src/soc/litex/florent/ls180soc.py @@ -372,14 +372,6 @@ class LibreSoCSim(SoCCore): #ram_init = [] - if False: - # for niolib temporary hack - io_in = Signal() - io_out = Signal() - - self.comb += io_in.eq(self.cpu.io_in) - self.comb += io_out.eq(self.cpu.io_out) - # SDRAM ---------------------------------------------------- if with_sdram: sdram_clk_freq = int(100e6) # FIXME: use 100MHz timings -- 2.30.2