From 63f095b29823628a9c89959358c9ea05e6080bd4 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 25 Jun 2022 16:53:30 +0100 Subject: [PATCH] --- openpower/sv/vector_ops.mdwn | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/openpower/sv/vector_ops.mdwn b/openpower/sv/vector_ops.mdwn index c510bcc4b..cdda04758 100644 --- a/openpower/sv/vector_ops.mdwn +++ b/openpower/sv/vector_ops.mdwn @@ -39,9 +39,9 @@ BM2-Form |0..5 |6..10|11..15|16..20|21-25|26|27..31| Form | |------|-----|------|------|-----|--|------|------| -| PO | RS | RA | RB |mode |L | XO | BM2-Form | +| PO | RS | RA | RB |bm |L | XO | BM2-Form | -* bmask RT,RA,RB,mode,L +* bmask RT,RA,RB,bm,L The patterns within the pseudocode for AMD TBM and x86 BMI1 are as follows: @@ -52,8 +52,10 @@ as follows: Thus it makes sense to create a single instruction that covers all of these. A crucial addition that is essential -for Scalable Vector usage however is the second mask parameter -(RB). +for Scalable Vector usage as Predicate Masks, is the second mask parameter +(RB). The additional paramater, L, if set, will leave bits of RA masked +by RB unaltered, otherwise those bits are set to zero. Note that when `RB=0` +then instead of reading from the register file the mask is set to all ones. Executable pseudocode demo: -- 2.30.2