From 63f28fc916c381075dd7f7c269eabea8312bdef8 Mon Sep 17 00:00:00 2001 From: Staf Verhaegen Date: Thu, 22 Apr 2021 15:38:33 +0200 Subject: [PATCH] Revert "add code-comments regarding potential use of FFSynchroniser" This reverts commit 269255360f8762066ddef51d7ee86d07bd168f80. Reason for reverting is that I documented upstream why FFSynchronizer is not used. https://gitlab.com/Chips4Makers/c4m-jtag/-/commit/b4aa89548fd7439eda24979ab7d8a516c22a360b --- c4m/nmigen/jtag/tap.py | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/c4m/nmigen/jtag/tap.py b/c4m/nmigen/jtag/tap.py index 77034cb..a72c89a 100755 --- a/c4m/nmigen/jtag/tap.py +++ b/c4m/nmigen/jtag/tap.py @@ -510,7 +510,6 @@ class TAP(Elaboratable): with m.State("READACK"): with m.If(dmi.ack_o): # Store read data in sr_data.i hold till next read - # Note: could use FFSynchroniser cd += sr_data.i.eq(dmi.dout) m.next = "IDLE" @@ -663,7 +662,6 @@ class TAP(Elaboratable): # clockdomain latch update in `domain` clockdomain and see when # it has falling edge. # At that edge put isir in sr.oe for one `domain` clockdomain - # Note: could use FFSynchroniser instead update_core = Signal(name=sr.name+"_update_core") update_core_prev = Signal(name=sr.name+"_update_core_prev") m.d[domain] += [ @@ -680,7 +678,6 @@ class TAP(Elaboratable): with m.If(sr_shift): m.d.posjtag += reg.eq(Cat(reg[1:], self.bus.tdi)) with m.If(sr_capture): - # could also use FFSynchroniser here too m.d.posjtag += reg.eq(sr.i) # tdo = reg[0], tdo_en = shift @@ -779,8 +776,8 @@ class TAP(Elaboratable): m.next = "READACK" with m.State("READACK"): with m.If(wb.ack): - # Store read data in sr_data.i and keep it there - # til next read. could use FFSynchroniser (see above) + # Store read data in sr_data.i + # and keep it there til next read m.d[domain] += sr_data.i.eq(wb.dat_r) m.next = "IDLE" with m.State("WRITEREAD"): -- 2.30.2