From 64087f35f6b1e10429615836ec9077b55e8e85fd Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 22 Jul 2020 15:48:18 +0100 Subject: [PATCH] field number ordering wrong way round? see https://bugs.libre-soc.org/show_bug.cgi?id=325#c107 --- src/soc/fu/trap/formal/proof_main_stage.py | 5 +++++ src/soc/fu/trap/main_stage.py | 2 ++ 2 files changed, 7 insertions(+) diff --git a/src/soc/fu/trap/formal/proof_main_stage.py b/src/soc/fu/trap/formal/proof_main_stage.py index 511ad9cb..6f24bd19 100644 --- a/src/soc/fu/trap/formal/proof_main_stage.py +++ b/src/soc/fu/trap/formal/proof_main_stage.py @@ -182,10 +182,15 @@ class Driver(Elaboratable): comb += expected_msr[MSR.PR].eq(0) comb += expected_msr[MSR.FP].eq(0) comb += expected_msr[MSR.PMM].eq(0) + # TODO: check ordering (which is smaller, which is larger) + # MSR.TSs or MSR.TSe+1? comb += expected_msr[MSR.TEs:MSR.TEe+1].eq(0) comb += expected_msr[MSR.UND].eq(0) comb += expected_msr[MSR.LE].eq(1) + # TODO: check ordering (which is smaller, which is larger) + # MSR.TSs or MSR.TSe+1? + # see https://bugs.libre-soc.org/show_bug.cgi?id=325#c107 with m.If(op.msr[MSR.TSs:MSR.TSe+1] == 0b10): comb += expected_msr[MSR.TSs:MSR.TSe+1].eq(0b01) with m.Else(): diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py index 548e0cfb..e41ccce1 100644 --- a/src/soc/fu/trap/main_stage.py +++ b/src/soc/fu/trap/main_stage.py @@ -103,6 +103,8 @@ class TrapMainStage(PipeModBase): comb += msr_o.data[MSR.VEC].eq(0) comb += msr_o.data[MSR.FP].eq(0) comb += msr_o.data[MSR.PMM].eq(0) + # XXX check ordering + # see https://bugs.libre-soc.org/show_bug.cgi?id=325#c107 comb += msr_o.data[MSR.TEs:MSR.TEe+1].eq(0) comb += msr_o.data[MSR.UND].eq(0) if msr_hv is not None: -- 2.30.2