From 642671b29daac5b510d9dba549c197aae80b80d9 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 17 Jan 2021 21:05:11 -0800 Subject: [PATCH] riscv: Export the system call ABI for use in gem5 ops. This ABI is effectively used by both the gem5 ops and system calls, in system calls because it only relies on registers, and in gem5 ops by inheritance. Even though these ABIs happen to be the same and were initially defined to be the same, this change creates a root "reg" ABI which will act as a root for both so that there isn't an implication that changes to one should be changes to both. Change-Id: I8726d8628503be2ad7616a71cc48b66f13e7d955 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39318 Reviewed-by: Jason Lowe-Power Reviewed-by: Ayaz Akram Maintainer: Gabe Black Tested-by: kokoro --- src/arch/riscv/SConscript | 2 +- src/arch/riscv/isa/formats/m5ops.isa | 11 ++--- src/arch/riscv/isa/includes.isa | 1 + src/arch/riscv/{se_workload.cc => reg_abi.cc} | 6 +-- src/arch/riscv/reg_abi.hh | 46 +++++++++++++++++++ src/arch/riscv/registers.hh | 3 -- src/arch/riscv/se_workload.hh | 7 +-- 7 files changed, 57 insertions(+), 19 deletions(-) rename src/arch/riscv/{se_workload.cc => reg_abi.cc} (92%) create mode 100644 src/arch/riscv/reg_abi.hh diff --git a/src/arch/riscv/SConscript b/src/arch/riscv/SConscript index 0179fbcd4..472264f25 100644 --- a/src/arch/riscv/SConscript +++ b/src/arch/riscv/SConscript @@ -51,8 +51,8 @@ if env['TARGET_ISA'] == 'riscv': Source('process.cc') Source('pagetable.cc') Source('pagetable_walker.cc') + Source('reg_abi.cc') Source('remote_gdb.cc') - Source('se_workload.cc') Source('tlb.cc') Source('linux/se_workload.cc') diff --git a/src/arch/riscv/isa/formats/m5ops.isa b/src/arch/riscv/isa/formats/m5ops.isa index 11834f67b..986438b0e 100644 --- a/src/arch/riscv/isa/formats/m5ops.isa +++ b/src/arch/riscv/isa/formats/m5ops.isa @@ -36,12 +36,11 @@ def format M5Op() {{ - iop = InstObjParams(name, Name, 'PseudoOp', - 'uint64_t result;\n' - 'PseudoInst::pseudoInst(' - 'xc->tcBase(), M5FUNC, result);\n' - 'a0 = result', - ['IsNonSpeculative', 'IsSerializeAfter']) + iop = InstObjParams(name, Name, 'PseudoOp', ''' + uint64_t result; + PseudoInst::pseudoInst(xc->tcBase(), M5FUNC, result); + a0 = result''', + ['IsNonSpeculative', 'IsSerializeAfter']) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) decode_block = BasicDecode.subst(iop) diff --git a/src/arch/riscv/isa/includes.isa b/src/arch/riscv/isa/includes.isa index d77d68e44..799559a25 100644 --- a/src/arch/riscv/isa/includes.isa +++ b/src/arch/riscv/isa/includes.isa @@ -81,6 +81,7 @@ output exec {{ #include "arch/generic/memhelpers.hh" #include "arch/riscv/faults.hh" #include "arch/riscv/mmu.hh" +#include "arch/riscv/reg_abi.hh" #include "arch/riscv/registers.hh" #include "arch/riscv/utility.hh" #include "base/condcodes.hh" diff --git a/src/arch/riscv/se_workload.cc b/src/arch/riscv/reg_abi.cc similarity index 92% rename from src/arch/riscv/se_workload.cc rename to src/arch/riscv/reg_abi.cc index ce4679c69..25aee6f8f 100644 --- a/src/arch/riscv/se_workload.cc +++ b/src/arch/riscv/reg_abi.cc @@ -25,13 +25,11 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include "arch/riscv/se_workload.hh" +#include "arch/riscv/reg_abi.hh" namespace RiscvISA { -const std::vector SEWorkload::SyscallABI::ArgumentRegs = { - 10, 11, 12, 13, 14, 15, 16 -}; +const std::vector RegABI64::ArgumentRegs = {10, 11, 12, 13, 14, 15, 16}; } // namespace RiscvISA diff --git a/src/arch/riscv/reg_abi.hh b/src/arch/riscv/reg_abi.hh new file mode 100644 index 000000000..492c117fc --- /dev/null +++ b/src/arch/riscv/reg_abi.hh @@ -0,0 +1,46 @@ +/* + * Copyright 2020 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ARCH_RISCV_REG_ABI_HH__ +#define __ARCH_RISCV_REG_ABI_HH__ + +#include + +#include "sim/syscall_abi.hh" + +namespace RiscvISA +{ + +//FIXME RISCV needs to handle 64 bit arguments in its 32 bit ISA. +struct RegABI64 : public GenericSyscallABI64 +{ + static const std::vector ArgumentRegs; +}; + +} // namespace RiscvISA + +#endif // __ARCH_RISCV_REG_ABI_HH__ diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh index 84a19249e..97216359f 100644 --- a/src/arch/riscv/registers.hh +++ b/src/arch/riscv/registers.hh @@ -93,11 +93,8 @@ const int NumCCRegs = 0; const int ZeroReg = 0; const int ReturnAddrReg = 1; const int StackPointerReg = 2; -const int GlobalPointerReg = 3; const int ThreadPointerReg = 4; -const int FramePointerReg = 8; const int ReturnValueReg = 10; -const std::vector ReturnValueRegs = {10, 11}; const std::vector ArgumentRegs = {10, 11, 12, 13, 14, 15, 16, 17}; const int AMOTempReg = 32; diff --git a/src/arch/riscv/se_workload.hh b/src/arch/riscv/se_workload.hh index e0be5a14a..d6df19ce3 100644 --- a/src/arch/riscv/se_workload.hh +++ b/src/arch/riscv/se_workload.hh @@ -28,11 +28,11 @@ #ifndef __ARCH_RISCV_SE_WORKLOAD_HH__ #define __ARCH_RISCV_SE_WORKLOAD_HH__ +#include "arch/riscv/reg_abi.hh" #include "arch/riscv/registers.hh" #include "params/RiscvSEWorkload.hh" #include "sim/se_workload.hh" #include "sim/syscall_abi.hh" -#include "sim/syscall_desc.hh" namespace RiscvISA { @@ -53,10 +53,7 @@ class SEWorkload : public ::SEWorkload ::Loader::Arch getArch() const override { return ::Loader::Riscv64; } //FIXME RISCV needs to handle 64 bit arguments in its 32 bit ISA. - struct SyscallABI : public GenericSyscallABI64 - { - static const std::vector ArgumentRegs; - }; + using SyscallABI = RegABI64; }; } // namespace RiscvISA -- 2.30.2