From 644fa8ec55e701a901de404d40e4ecf9b17c04bd Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 1 Sep 2014 23:11:40 +0200 Subject: [PATCH] kc705: enable DCI termination on DDR3 --- mibuild/platforms/kc705.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/mibuild/platforms/kc705.py b/mibuild/platforms/kc705.py index 2df33eb2..696055f8 100644 --- a/mibuild/platforms/kc705.py +++ b/mibuild/platforms/kc705.py @@ -109,7 +109,7 @@ _io = [ "AH5 AH6 AJ2 AH2 AH4 AJ4 AK1 AJ1", "AF1 AF2 AE4 AE3 AF3 AF5 AE1 AE5", "AC1 AD3 AC4 AC5 AE6 AD6 AC2 AD4"), - IOStandard("SSTL15")), + IOStandard("SSTL15_T_DCI")), Subsignal("dqs_p", Pins("AC16 Y19 AJ18 AH16 AH7 AG2 AG4 AD2"), IOStandard("DIFF_SSTL15")), Subsignal("dqs_n", Pins("AC15 Y18 AK18 AJ16 AJ7 AH1 AG3 AD1"), @@ -150,4 +150,8 @@ def Platform(*args, toolchain="vivado", **kwargs): self.add_period_constraint(self.lookup_request("clk200").p, 5.0) except ConstraintError: pass + if isinstance(self, XilinxISEPlatform): + self.add_platform_command("CONFIG DCI_CASCADE = \"33 32 34\";") + else: + self.add_platform_command("set_property DCI_CASCADE {{32 34}} [get_iobanks 33]") return RealPlatform(*args, **kwargs) -- 2.30.2