From 6451008e8b6013351e3e7e26f6827a218a76fcb3 Mon Sep 17 00:00:00 2001 From: Nanley Chery Date: Mon, 7 Oct 2019 15:48:33 -0700 Subject: [PATCH] intel: Refactor blorp_can_hiz_clear_depth() Prepare this function to be used in iris and to handle new Gen12 behavior. Reviewed-by: Sagar Ghuge Reviewed-by: Kenneth Graunke --- src/intel/blorp/blorp.h | 9 +++++---- src/intel/blorp/blorp_clear.c | 15 +++++++++------ src/intel/vulkan/genX_cmd_buffer.c | 11 +++++------ 3 files changed, 19 insertions(+), 16 deletions(-) diff --git a/src/intel/blorp/blorp.h b/src/intel/blorp/blorp.h index df48e91cecc..ead261b6230 100644 --- a/src/intel/blorp/blorp.h +++ b/src/intel/blorp/blorp.h @@ -188,10 +188,11 @@ blorp_clear_depth_stencil(struct blorp_batch *batch, bool clear_depth, float depth_value, uint8_t stencil_mask, uint8_t stencil_value); bool -blorp_can_hiz_clear_depth(uint8_t gen, enum isl_format format, - uint32_t num_samples, - uint32_t x0, uint32_t y0, - uint32_t x1, uint32_t y1); +blorp_can_hiz_clear_depth(const struct gen_device_info *devinfo, + const struct isl_surf *surf, + enum isl_aux_usage aux_usage, + uint32_t level, uint32_t layer, + uint32_t x0, uint32_t y0, uint32_t x1, uint32_t y1); void blorp_hiz_clear_depth_stencil(struct blorp_batch *batch, const struct blorp_surf *depth, diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c index 7f5ae8ae358..6034bdac413 100644 --- a/src/intel/blorp/blorp_clear.c +++ b/src/intel/blorp/blorp_clear.c @@ -754,14 +754,16 @@ blorp_clear_depth_stencil(struct blorp_batch *batch, } bool -blorp_can_hiz_clear_depth(uint8_t gen, enum isl_format format, - uint32_t num_samples, +blorp_can_hiz_clear_depth(const struct gen_device_info *devinfo, + const struct isl_surf *surf, + enum isl_aux_usage aux_usage, + uint32_t level, uint32_t layer, uint32_t x0, uint32_t y0, uint32_t x1, uint32_t y1) { /* This function currently doesn't support any gen prior to gen8 */ - assert(gen >= 8); + assert(devinfo->gen >= 8); - if (gen == 8 && format == ISL_FORMAT_R16_UNORM) { + if (devinfo->gen == 8 && surf->format == ISL_FORMAT_R16_UNORM) { /* Apply the D16 alignment restrictions. On BDW, HiZ has an 8x4 sample * block with the following property: as the number of samples increases, * the number of pixels representable by this block decreases by a factor @@ -780,7 +782,7 @@ blorp_can_hiz_clear_depth(uint8_t gen, enum isl_format format, * Table: Pixel Dimensions in a HiZ Sample Block Pre-SKL */ const struct isl_extent2d sa_block_dim = - isl_get_interleaved_msaa_px_size_sa(num_samples); + isl_get_interleaved_msaa_px_size_sa(surf->samples); const uint8_t align_px_w = 8 / sa_block_dim.w; const uint8_t align_px_h = 4 / sa_block_dim.h; @@ -801,7 +803,8 @@ blorp_can_hiz_clear_depth(uint8_t gen, enum isl_format format, x1 % align_px_w || y1 % align_px_h) return false; } - return true; + + return isl_aux_usage_has_hiz(aux_usage); } void diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index d8afe578105..16ebcacf8f0 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -419,12 +419,11 @@ depth_stencil_attachment_compute_aux_usage(struct anv_device *device, anv_layout_to_aux_usage(&device->info, iview->image, VK_IMAGE_ASPECT_DEPTH_BIT, pass_att->first_subpass_layout); - if (first_subpass_aux_usage != ISL_AUX_USAGE_HIZ) - return; - - if (!blorp_can_hiz_clear_depth(GEN_GEN, - iview->planes[0].isl.format, - iview->image->samples, + if (!blorp_can_hiz_clear_depth(&device->info, + &iview->image->planes[0].surface.isl, + first_subpass_aux_usage, + iview->planes[0].isl.base_level, + iview->planes[0].isl.base_array_layer, render_area.offset.x, render_area.offset.y, render_area.offset.x + -- 2.30.2