From 645fa42ac8d6f8f9cc744e89e6af807df2eca38a Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 5 Jul 2022 19:01:30 +0100 Subject: [PATCH] converted test_caller_svp64_matrix.py to new reg format https://bugs.libre-soc.org/show_bug.cgi?id=884#c0 --- src/openpower/decoder/isa/test_caller_svp64_matrix.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/openpower/decoder/isa/test_caller_svp64_matrix.py b/src/openpower/decoder/isa/test_caller_svp64_matrix.py index 130f9472..43f14c8e 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_matrix.py +++ b/src/openpower/decoder/isa/test_caller_svp64_matrix.py @@ -28,13 +28,13 @@ class DecoderTestCase(FHDLTestCase): def test_sv_remap1(self): """>>> lst = ["svshape 2, 2, 3, 0, 0", "svremap 31, 1, 2, 3, 0, 0, 0", - "sv.fmadds 0.v, 8.v, 16.v, 0.v" + "sv.fmadds *0, *8, *16, *0" ] REMAP fmadds FRT, FRA, FRC, FRB """ lst = SVP64Asm(["svshape 2, 2, 3, 0, 0", "svremap 31, 1, 2, 3, 0, 0, 0", - "sv.fmadds 0.v, 16.v, 32.v, 0.v" + "sv.fmadds *0, *16, *32, *0" ]) lst = list(lst) @@ -94,13 +94,13 @@ class DecoderTestCase(FHDLTestCase): def test_sv_remap2(self): """>>> lst = ["svshape 5, 4, 3, 0, 0", "svremap 31, 1, 2, 3, 0, 0, 0", - "sv.fmadds 0.v, 8.v, 16.v, 0.v" + "sv.fmadds *0, *8, *16, *0" ] REMAP fmadds FRT, FRA, FRC, FRB """ lst = SVP64Asm(["svshape 4, 3, 3, 0, 0", "svremap 31, 1, 2, 3, 0, 0, 0", - "sv.fmadds 0.v, 16.v, 32.v, 0.v" + "sv.fmadds *0, *16, *32, *0" ]) lst = list(lst) -- 2.30.2