From 64972360a82dcce0c786c2f2e0c3c72cde76af5a Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 11 Jan 2022 08:21:12 +0100 Subject: [PATCH] Update CHANGELOG --- CHANGELOG | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index c878b3c1c..c10b54d44 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -3,17 +3,14 @@ List of major changes and improvements between releases ======================================================= Yosys 0.12 .. Yosys 0.12-dev --------------------------- - -Yosys 0.11 .. Yosys 0.12 -------------------------- * Various - - Added iopadmap native support for negative-polarity output enable - - ABC update + - Use "read" command to parse HDL files from Yosys command-line + - Added "yosys -r " command line option + - write_verilog: dump zero width sigspecs correctly * SystemVerilog - - Support parameters using struct as a wiretype - Fixed regression preventing the use array querying functions in case expressions and case item expressions - Fixed static size casts inadvertently limiting the result width of binary @@ -24,6 +21,22 @@ Yosys 0.11 .. Yosys 0.12 procedures which are always assigned before they are used to avoid errant latch inference + * New commands and options + - Added "clean_zerowidth" pass + + * Verific support + - Add YOSYS to the implicitly defined verilog macros in verific + +Yosys 0.11 .. Yosys 0.12 +-------------------------- + + * Various + - Added iopadmap native support for negative-polarity output enable + - ABC update + + * SystemVerilog + - Support parameters using struct as a wiretype + * New commands and options - Added "-genlib" option to "abc" pass - Added "sta" very crude static timing analysis pass -- 2.30.2