From 649dc663a7c10fb82783c575b3ee5c4c7d39571b Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 9 Oct 2020 14:20:07 +0100 Subject: [PATCH] --- HDL_workflow.mdwn | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/HDL_workflow.mdwn b/HDL_workflow.mdwn index 6530120ff..0eb4cfa47 100644 --- a/HDL_workflow.mdwn +++ b/HDL_workflow.mdwn @@ -431,9 +431,9 @@ See [[HDL_workflow/coriolis2]] page, for those people doing layout work. ## Chips4Makers JTAG -As this is an actual ASIC, we do not rely on an FPGA's JTAG TAP interface, instead require a full complete independent implementation of JTAG. Staf Verhaegen has one, with a full test suite, and it is superb and well-written. +As this is an actual ASIC, we do not rely on an FPGA's JTAG TAP interface, instead require a full complete independent implementation of JTAG. Staf Verhaegen has one, with a full test suite, and it is superb and well-written. The Libre-SOC version includes DMI (Debug Memory Interface): - git clone https://gitlab.com/Chips4Makers/c4m-jtag.git + git clone https://git.libre-soc.org/c4m-jtag.git Included is an IDCODE tap point, Wishbone Master (for direct memory read and write, fully independent of the core), IOPad redirection and testing, and general purpose shift register capability for any custom use. -- 2.30.2