From 64ace0cbcb3ae16dbce98240f1d9fcdae8869a41 Mon Sep 17 00:00:00 2001 From: Jean THOMAS Date: Fri, 3 Jul 2020 14:55:20 +0200 Subject: [PATCH] Add tests in DFI Injector for odt and reset signals --- gram/test/test_dfii.py | 30 +++++++++++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) diff --git a/gram/test/test_dfii.py b/gram/test/test_dfii.py index 27543f7..475e980 100644 --- a/gram/test/test_dfii.py +++ b/gram/test/test_dfii.py @@ -120,7 +120,7 @@ class PhaseInjectorTestCase(FHDLTestCase): class DFIInjectorTestCase(FHDLTestCase): def generate_dfiinjector(self): csrhost = CSRHost() - dut = DFIInjector(csrhost.bank, 14, 3, 1, 16, nphases=1) + dut = DFIInjector(csrhost.bank, addressbits=14, bankbits=3, nranks=1, databits=16, nphases=1) csrhost.init_bridge() m = Module() m.submodules += csrhost @@ -141,3 +141,31 @@ class DFIInjectorTestCase(FHDLTestCase): self.assertFalse((yield dut.master.phases[0].cke[0])) runSimulation(m, process, "test_dfiinjector.vcd") + + def test_odt(self): + m, dut, csrhost = self.generate_dfiinjector() + + def process(): + yield from wb_write(csrhost.bus, DFII_CONTROL_ADDR >> 2, (1 << 2), sel=0xF) + yield + self.assertTrue((yield dut.master.phases[0].odt[0])) + + yield from wb_write(csrhost.bus, DFII_CONTROL_ADDR >> 2, 0, sel=0xF) + yield + self.assertFalse((yield dut.master.phases[0].odt[0])) + + runSimulation(m, process, "test_dfiinjector.vcd") + + def test_reset(self): + m, dut, csrhost = self.generate_dfiinjector() + + def process(): + yield from wb_write(csrhost.bus, DFII_CONTROL_ADDR >> 2, (1 << 3), sel=0xF) + yield + self.assertTrue((yield dut.master.phases[0].reset_n)) + + yield from wb_write(csrhost.bus, DFII_CONTROL_ADDR >> 2, 0, sel=0xF) + yield + self.assertFalse((yield dut.master.phases[0].reset_n)) + + runSimulation(m, process, "test_dfiinjector.vcd") -- 2.30.2