From 64ce64a3f88f0c33a3f9a97f231bd98983887e27 Mon Sep 17 00:00:00 2001 From: Paul Berry Date: Fri, 23 Sep 2011 21:36:17 -0700 Subject: [PATCH] i965 new VS: Fix bugs in pre-GEN6 psiz/flags computation This patch corrects two errors in the computation of the psiz/flags VUE slot on pre-GEN5 when using the new VS backend: - The clip flags (which should be stored in the w component of the first VUE slot) were being accidentally duplicated in all other components of that VUE slot, causing partially clipped triangles to sometimes disappear completely. - The OR instruction wasn't being stored in "inst", causing the BRW_PREDICATE_NORMAL flag to be applied to the wrong instruction. This patch fixes regressions in clipping behavior when using shaders on GEN4-5. Reviewed-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp index ee3b2a8ba5c..e5eda221044 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp @@ -1767,6 +1767,8 @@ vec4_visitor::emit_psiz_and_flags(struct brw_reg reg) ((c->prog_data.outputs_written & BITFIELD64_BIT(VERT_RESULT_PSIZ)) || c->key.nr_userclip || brw->has_negative_rhw_bug)) { dst_reg header1 = dst_reg(this, glsl_type::uvec4_type); + dst_reg header1_w = header1; + header1_w.writemask = WRITEMASK_W; GLuint i; emit(MOV(header1, 0u)); @@ -1775,9 +1777,8 @@ vec4_visitor::emit_psiz_and_flags(struct brw_reg reg) src_reg psiz = src_reg(output_reg[VERT_RESULT_PSIZ]); current_annotation = "Point size"; - header1.writemask = WRITEMASK_W; - emit(MUL(header1, psiz, src_reg((float)(1 << 11)))); - emit(AND(header1, src_reg(header1), 0x7ff << 8)); + emit(MUL(header1_w, psiz, src_reg((float)(1 << 11)))); + emit(AND(header1_w, src_reg(header1_w), 0x7ff << 8)); } current_annotation = "Clipping flags"; @@ -1788,7 +1789,7 @@ vec4_visitor::emit_psiz_and_flags(struct brw_reg reg) src_reg(this->userplane[i]))); inst->conditional_mod = BRW_CONDITIONAL_L; - emit(OR(header1, src_reg(header1), 1u << i)); + inst = emit(OR(header1_w, src_reg(header1_w), 1u << i)); inst->predicate = BRW_PREDICATE_NORMAL; } @@ -1816,7 +1817,6 @@ vec4_visitor::emit_psiz_and_flags(struct brw_reg reg) #endif } - header1.writemask = WRITEMASK_XYZW; emit(MOV(retype(reg, BRW_REGISTER_TYPE_UD), src_reg(header1))); } else if (intel->gen < 6) { emit(MOV(retype(reg, BRW_REGISTER_TYPE_UD), 0u)); -- 2.30.2