From 64d77460b733e8537b58ef9a3eb725dbd668fec6 Mon Sep 17 00:00:00 2001
From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Mon, 20 Jul 2020 18:23:18 +0200
Subject: [PATCH] Remove DQSPattern

---
 gram/common.py           | 31 -------------------------------
 gram/test/test_common.py | 25 -------------------------
 2 files changed, 56 deletions(-)

diff --git a/gram/common.py b/gram/common.py
index bea610d..0c0503b 100644
--- a/gram/common.py
+++ b/gram/common.py
@@ -60,37 +60,6 @@ def get_sys_phases(nphases, sys_latency, cas_latency):
     cmd_phase = (dat_phase - 1) % nphases
     return cmd_phase, dat_phase
 
-class DQSPattern(Elaboratable):
-    def __init__(self, preamble=Signal(), postamble=Signal(), wlevel_en=0, wlevel_strobe=0, register=False):
-        self.preamble = preamble
-        self.postamble = postamble
-        self.o = Signal(8)
-        self._wlevel_en = wlevel_en
-        self._wlevel_strobe = wlevel_strobe
-        self._register = register
-
-    def elaborate(self, platform):
-        m = Module()
-
-        with m.If(self.preamble):
-            m.d.comb += self.o.eq(0b00010101)
-        with m.Elif(self.postamble):
-            m.d.comb += self.o.eq(0b01010100)
-        with m.Elif(self._wlevel_en):
-            with m.If(self._wlevel_strobe):
-                m.d.comb += self.o.eq(0b00000001)
-            with m.Else():
-                m.d.comb += self.o.eq(0b00000000)
-        with m.Else():
-            m.d.comb += self.o.eq(0b01010101)
-
-        if self._register:
-            o = Signal.like(self.o)
-            m.d.sync += o.eq(self.o)
-            self.o = o
-
-        return m
-
 # Settings -----------------------------------------------------------------------------------------
 
 
diff --git a/gram/test/test_common.py b/gram/test/test_common.py
index a051f1a..5f954ca 100644
--- a/gram/test/test_common.py
+++ b/gram/test/test_common.py
@@ -5,31 +5,6 @@ from nmigen.hdl.ast import Past
 from gram.common import DQSPattern, tXXDController
 from utils import *
 
-class DQSPatternTestCase(FHDLTestCase):
-    def test_async(self):
-        m = Module()
-        m.d.sync += Signal().eq(0) # Workaround for nMigen#417
-        m.submodules.dut = dut = DQSPattern(register=False)
-
-        def process():
-            yield dut.preamble.eq(1) # Preamble=1, Postamble=0
-            yield
-            self.assertEqual((yield dut.o), 0b00010101)
-
-            yield dut.postamble.eq(1) # Preamble=1, Postamble=1
-            yield
-            self.assertEqual((yield dut.o), 0b00010101)
-
-            yield dut.preamble.eq(0) # Preamble=0, Postamble=1
-            yield
-            self.assertEqual((yield dut.o), 0b01010100)
-
-            yield dut.postamble.eq(0) # Preamble=1, Postamble=1
-            yield
-            self.assertEqual((yield dut.o), 0b01010101)
-
-        runSimulation(m, process, "test_dqspattern_async.vcd")
-
 class tXXDControllerTestCase(FHDLTestCase):
     def test_formal(self):
         def generic_test(txxd):
-- 
2.30.2