From 64fd5f375c11694d4093837b10f6bdd7c8b8db7f Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 2 May 2016 15:11:25 -0700 Subject: [PATCH] Remove MIPI; mip.MSIP bit is read-only --- riscv/encoding.h | 6 ------ riscv/processor.cc | 8 ++------ 2 files changed, 2 insertions(+), 12 deletions(-) diff --git a/riscv/encoding.h b/riscv/encoding.h index 5cb7ff5..5405148 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -661,7 +661,6 @@ #define CSR_MCAUSE 0x342 #define CSR_MBADADDR 0x343 #define CSR_MIP 0x344 -#define CSR_MIPI 0x345 #define CSR_MUCOUNTEREN 0x310 #define CSR_MSCOUNTEREN 0x311 #define CSR_MUCYCLE_DELTA 0x700 @@ -678,8 +677,6 @@ #define CSR_MARCHID 0xf12 #define CSR_MIMPID 0xf13 #define CSR_MHARTID 0xf14 -#define CSR_MTOHOST 0x7c0 -#define CSR_MFROMHOST 0x7c1 #define CSR_MRESET 0x7c2 #define CSR_CYCLEH 0xc80 #define CSR_TIMEH 0xc81 @@ -966,7 +963,6 @@ DECLARE_CSR(mepc, CSR_MEPC) DECLARE_CSR(mcause, CSR_MCAUSE) DECLARE_CSR(mbadaddr, CSR_MBADADDR) DECLARE_CSR(mip, CSR_MIP) -DECLARE_CSR(mipi, CSR_MIPI) DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN) DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN) DECLARE_CSR(mucycle_delta, CSR_MUCYCLE_DELTA) @@ -983,8 +979,6 @@ DECLARE_CSR(mvendorid, CSR_MVENDORID) DECLARE_CSR(marchid, CSR_MARCHID) DECLARE_CSR(mimpid, CSR_MIMPID) DECLARE_CSR(mhartid, CSR_MHARTID) -DECLARE_CSR(mtohost, CSR_MTOHOST) -DECLARE_CSR(mfromhost, CSR_MFROMHOST) DECLARE_CSR(mreset, CSR_MRESET) DECLARE_CSR(cycleh, CSR_CYCLEH) DECLARE_CSR(timeh, CSR_TIMEH) diff --git a/riscv/processor.cc b/riscv/processor.cc index 6eb5ddb..8714b97 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -254,7 +254,7 @@ static bool validate_vm(int max_xlen, reg_t vm) void processor_t::set_csr(int which, reg_t val) { val = zext_xlen(val); - reg_t delegable_ints = MIP_SSIP | MIP_STIP | (1 << IRQ_HOST) | (1 << IRQ_COP); + reg_t delegable_ints = MIP_SSIP | MIP_STIP | (1 << IRQ_COP); reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP; switch (which) { @@ -300,13 +300,10 @@ void processor_t::set_csr(int which, reg_t val) break; } case CSR_MIP: { - reg_t mask = MIP_SSIP | MIP_STIP | MIP_MSIP; + reg_t mask = MIP_SSIP | MIP_STIP; state.mip = (state.mip & ~mask) | (val & mask); break; } - case CSR_MIPI: - state.mip = set_field(state.mip, MIP_MSIP, val & 1); - break; case CSR_MIE: state.mie = (state.mie & ~all_ints) | (val & all_ints); break; @@ -424,7 +421,6 @@ reg_t processor_t::get_csr(int which) case CSR_SSCRATCH: return state.sscratch; case CSR_MSTATUS: return state.mstatus; case CSR_MIP: return state.mip; - case CSR_MIPI: return 0; case CSR_MIE: return state.mie; case CSR_MEPC: return state.mepc; case CSR_MSCRATCH: return state.mscratch; -- 2.30.2