From 650332b3d832790e72cc48c99f20c247e8cd858b Mon Sep 17 00:00:00 2001 From: Staf Verhaegen Date: Fri, 5 Jun 2020 18:44:50 +0200 Subject: [PATCH] [libre-riscv-dev] NLNet018TV documentation --- 9c/7f02d9ed18d9f0e8e80601b6b9abde930286bb | 116 ++++++++++++++++++++++ 1 file changed, 116 insertions(+) create mode 100644 9c/7f02d9ed18d9f0e8e80601b6b9abde930286bb diff --git a/9c/7f02d9ed18d9f0e8e80601b6b9abde930286bb b/9c/7f02d9ed18d9f0e8e80601b6b9abde930286bb new file mode 100644 index 0000000..6eadf1e --- /dev/null +++ b/9c/7f02d9ed18d9f0e8e80601b6b9abde930286bb @@ -0,0 +1,116 @@ +Return-path: +Envelope-to: publicinbox@libre-riscv.org +Delivery-date: Fri, 05 Jun 2020 17:45:01 +0100 +Received: from localhost ([::1] helo=libre-riscv.org) + by libre-soc.org with esmtp (Exim 4.89) + (envelope-from ) + id 1jhFSm-0005RR-BM; Fri, 05 Jun 2020 17:45:00 +0100 +Received: from vps2.stafverhaegen.be ([85.10.201.15]) + by libre-soc.org with esmtp (Exim 4.89) + (envelope-from ) id 1jhFSj-0005RF-Ul + for libre-riscv-dev@lists.libre-riscv.org; Fri, 05 Jun 2020 17:44:57 +0100 +Received: from hpdc7800 (hpdc7800 [10.0.0.1]) + by vps2.stafverhaegen.be (Postfix) with ESMTP id 2347D11C055D + for ; + Fri, 5 Jun 2020 18:44:57 +0200 (CEST) +Message-ID: +From: Staf Verhaegen +To: Libre RISC-V dev list +Date: Fri, 05 Jun 2020 18:44:50 +0200 +Organization: FibraServi bvba +X-Mailer: Evolution 3.28.5 (3.28.5-8.el7) +Mime-Version: 1.0 +X-Content-Filtered-By: Mailman/MimeDel 2.1.23 +Subject: [libre-riscv-dev] NLNet018TV documentation +X-BeenThere: libre-riscv-dev@lists.libre-riscv.org +X-Mailman-Version: 2.1.23 +Precedence: list +List-Id: Libre-RISCV General Development + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Reply-To: Libre-RISCV General Development + +Content-Type: multipart/mixed; boundary="===============4334940942924319424==" +Errors-To: libre-riscv-dev-bounces@lists.libre-riscv.org +Sender: "libre-riscv-dev" + + +--===============4334940942924319424== +Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; + boundary="=-cFXASkxalv2oLkrW/waf" + + +--=-cFXASkxalv2oLkrW/waf +Content-Type: text/plain; charset="UTF-8" +Content-Transfer-Encoding: quoted-printable + +Goodday all, + +I did tape-out the TSMC 0.18=C2=B5m test chip around a week ago and am now +hard at work in documenting was is on the chip. I just pushed first +version of the documentation and can be found in the designs/NLNet018TV + directory on my SnowWhite repo on gitlab. Currently it only discusses +what is on the design; not why these structures are there with this +design. This is planned for later. Next step is to add a test plan and +then blog about it. + +Most significant change is that I did not put a full SRAM block on the +design but single SRAM cells only. This was both due the limited +availability of IO pins and the time pressure of the tape-out deadline. +Instead more focus was put on the design of the IO cells which is +actually the main reason of this test chip. + +I did currently have three different drive strengths for the source and +sink drivers next to the pull-up/pull-down functionality. +The highest drive strength of 230mA is meant for driving resistive +loads like for example LEDS. The real current will most of the time be +limited by an external resistor in order to limit the heating of the +chip. This is one the things that will be measured during testing. +These test chips are wirebonded semi-manually and to ease it a pitch of +90=C2=B5m between the IO cells is used. The 230mA driver strength is the +result of filling up the total width of the IO cell with drivers. +Depending on the number of outputs for the prototype we may negotiate a +smaller pitch but this will also reduce the drive strength of this big +driver or alternatively the IO cell may need to be made higher. +The two lower drive strength are meant to drive capacitive loads. They +can be either used alone or combined giving possibility of having 10mA, +20mA or 30mA (e.g. 10mA + 20mA) drivers. It allows to configure them as +having the driver sink or source current or both. Reason I choose these +drive strengths is that the 10mA corresponds with one transistor needed +to fulfill the ESD design rules and in simulation I did see acceptable +output over/undershoot even with minimal capacitive load. From +simulation a 40mA driver gave significant overshoot/undershoot and +oscillation even with high capacitive loads. +The design of the IO cell is quite flexible and can still be adapted if +there would be special needs for the prototype. So I am interested to +know what changes you think are needed for the prototype. + +greets, +Staf. + + +--=-cFXASkxalv2oLkrW/waf-- + + + +--===============4334940942924319424== +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: base64 +Content-Disposition: inline + +X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KbGlicmUtcmlz +Y3YtZGV2IG1haWxpbmcgbGlzdApsaWJyZS1yaXNjdi1kZXZAbGlzdHMubGlicmUtcmlzY3Yub3Jn +Cmh0dHA6Ly9saXN0cy5saWJyZS1yaXNjdi5vcmcvbWFpbG1hbi9saXN0aW5mby9saWJyZS1yaXNj +di1kZXYK + +--===============4334940942924319424==-- + + + -- 2.30.2