From 6507ee86c014b70fac45578500fc87612403d664 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Sun, 4 Sep 2022 00:53:30 -0700 Subject: [PATCH] reallocate opcodes for ffadds (converted to X-FORM) and fdmadds to make space for fptrans --- openpower/isatables/RM-1P-2S1D.csv | 2 +- openpower/isatables/minor_59.csv | 4 ++-- src/openpower/decoder/isa/caller.py | 3 ++- src/openpower/decoder/power_decoder2.py | 16 ++++++++++------ src/openpower/sv/trans/svp64.py | 4 ++-- 5 files changed, 17 insertions(+), 12 deletions(-) diff --git a/openpower/isatables/RM-1P-2S1D.csv b/openpower/isatables/RM-1P-2S1D.csv index 0e155d5e..dc265695 100644 --- a/openpower/isatables/RM-1P-2S1D.csv +++ b/openpower/isatables/RM-1P-2S1D.csv @@ -91,11 +91,11 @@ divdo,NORMAL,,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 divwo,NORMAL,,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 grev,NORMAL,,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 grevw,NORMAL,,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 -ffadds,NORMAL,,1P,EXTRA3,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 fdivs,NORMAL,,1P,EXTRA3,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 fsubs,NORMAL,,1P,EXTRA3,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 fadds,NORMAL,,1P,EXTRA3,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 fmuls,NORMAL,,1P,EXTRA3,d:FRT;d:CR1,s:FRA,s:FRC,0,FRA,0,FRC,FRT,0,CR1,0 +ffadds,NORMAL,,1P,EXTRA3,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 fdiv,NORMAL,,1P,EXTRA3,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 fsub,NORMAL,,1P,EXTRA3,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 fadd,NORMAL,,1P,EXTRA3,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 diff --git a/openpower/isatables/minor_59.csv b/openpower/isatables/minor_59.csv index 0f0cb8d6..25214b44 100644 --- a/openpower/isatables/minor_59.csv +++ b/openpower/isatables/minor_59.csv @@ -18,7 +18,7 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou -----00101,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,ffmadds,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg -----00110,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,ffnmsubs,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg -----00111,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,ffnmadds,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg ------01101,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,ffadds,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg ------01111,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fdmadds,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg +1000001100,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,ffadds,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg +-----11011,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fdmadds,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg 1000001110,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fsins,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg 1000101110,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fcoss,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py index 2d8defab..7eb265e4 100644 --- a/src/openpower/decoder/isa/caller.py +++ b/src/openpower/decoder/isa/caller.py @@ -14,7 +14,7 @@ related bugs: """ import re -from nmigen.sim import Settle +from nmigen.sim import Settle, Delay from functools import wraps from copy import copy, deepcopy from openpower.decoder.orderedset import OrderedSet @@ -1686,6 +1686,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers): it is purely for skipping masked-out bits """ # get SVSTATE VL (oh and print out some debug stuff) + # yield Delay(1e-10) # make changes visible vl = self.svstate.vl subvl = yield self.dec2.rm_dec.rm_in.subvl srcstep = self.svstate.srcstep diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py index 9312e790..d6b1815a 100644 --- a/src/openpower/decoder/power_decoder2.py +++ b/src/openpower/decoder/power_decoder2.py @@ -1026,12 +1026,16 @@ class PowerDecodeSubset(Elaboratable): # likely with a sub-decoder. major = Signal(6) comb += major.eq(self.dec.opcode_in[26:32]) - xo5 = Signal(1) # 1 bit from Minor 59 XO field == 0b0XXXX - comb += xo5.eq(self.dec.opcode_in[5]) - xo = Signal(5) # 5 bits from Minor 59 fcfids == 0b01110 - comb += xo.eq(self.dec.opcode_in[1:6]) - comb += self.use_svp64_fft.eq((major == 59) & (xo5 == 0b0) & - (xo != 0b01110)) + xo = Signal(10) + comb += xo.eq(self.dec.opcode_in[1:11]) + comb += self.use_svp64_fft.eq((major == 59) & xo.matches( + '-----00100', # ffmsubs + '-----00101', # ffmadds + '-----00110', # ffnmsubs + '-----00111', # ffnmadds + '1000001100', # ffadds + '-----11011', # fdmadds + )) # decoded/selected instruction flags comb += self.do_copy("data_len", self.op_get("ldst_len")) diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py index e094392e..7d32cf7c 100644 --- a/src/openpower/sv/trans/svp64.py +++ b/src/openpower/sv/trans/svp64.py @@ -1375,7 +1375,7 @@ class SVP64Asm: opcode |= int(v30b_newfields[1]) << (32-16) # FRA opcode |= int(v30b_newfields[2]) << (32-21) # FRB opcode |= int(v30b_newfields[3]) << (32-26) # FRC - opcode |= 0b01111 << (32-31) # bits 26-30 + opcode |= 0b11011 << (32-31) # bits 26-30 if rc: opcode |= 1 # Rc, bit 31. yield ".long 0x%x" % opcode @@ -1385,7 +1385,7 @@ class SVP64Asm: opcode |= int(v30b_newfields[0]) << (32-11) # FRT opcode |= int(v30b_newfields[1]) << (32-16) # FRA opcode |= int(v30b_newfields[2]) << (32-21) # FRB - opcode |= 0b01101 << (32-31) # bits 26-30 + opcode |= 0b1000001100 << (32-31) # bits 21-30 if rc: opcode |= 1 # Rc, bit 31. yield ".long 0x%x" % opcode -- 2.30.2