From 6509973d997c745b615707015988e39df71f5424 Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Mon, 12 Sep 2022 18:39:42 +0200 Subject: [PATCH] add core_clk_freq variable --- src/ls2.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/ls2.py b/src/ls2.py index cb620c2..84ea1c3 100644 --- a/src/ls2.py +++ b/src/ls2.py @@ -253,6 +253,7 @@ class DDR3SoC(SoC, Elaboratable): xics_icp_addr=None, xics_ics_addr=None, clk_freq=50e6, dram_clk_freq=None, + core_clk_freq=50e6, add_cpu=True): # wishbone routing is as follows: @@ -365,6 +366,7 @@ class DDR3SoC(SoC, Elaboratable): dram_offset = ddr_addr if (ddr_pins is not None) else None self.syscon = MicrowattSYSCON(sys_clk_freq=clk_freq, mem_clk_freq=self.dram_clk_freq, + core_clk_freq=core_clk_freq, has_uart=(uart_pins is not None), spi_offset=spi_offset, dram_addr=dram_offset) @@ -888,6 +890,7 @@ def build_platform(fpga, firmware): clk_freq = 40.0e6 if fpga == 'orangecrab' or fpga=='orangecrab_isim': clk_freq = 50e6 + core_clk_freq = clk_freq # merge dram_clk_freq with clk_freq if the same if clk_freq == dram_clk_freq: @@ -1107,6 +1110,7 @@ def build_platform(fpga, firmware): xics_ics_addr=0xc000_5000, # XICS_ICS_BASE clk_freq=clk_freq, dram_clk_freq=dram_clk_freq, + core_clk_freq=core_clk_freq, add_cpu=True) if toolchain == 'Trellis': -- 2.30.2