From 650f5a4b572f10d3fd3ff3f211cfa7fe661dcded Mon Sep 17 00:00:00 2001 From: Cesar Strauss Date: Sat, 3 Apr 2021 08:07:51 -0300 Subject: [PATCH] Add twin predication test Another simulator failure. Seems like the VL loop is still not terminating properly. Will investigate. --- .../isa/test_caller_svp64_predication.py | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/src/soc/decoder/isa/test_caller_svp64_predication.py b/src/soc/decoder/isa/test_caller_svp64_predication.py index 96827e8a..94736736 100644 --- a/src/soc/decoder/isa/test_caller_svp64_predication.py +++ b/src/soc/decoder/isa/test_caller_svp64_predication.py @@ -370,6 +370,39 @@ class DecoderTestCase(FHDLTestCase): sim = self.run_tst_program(program, initial_regs, svstate) self._check_regs(sim, expected_regs) + def test_intpred_twinpred(self): + # reg num 0 1 2 3 4 5 6 7 8 9 10 11 + # src r3=0b101 Y N Y + # | + # +-----+ + # | + # dest ~r3=0b010 N Y N + + isa = SVP64Asm(['sv.extsb/sm=r3/dm=~r3 5.v, 9.v']) + lst = list(isa) + print("listing", lst) + + # initial values in GPR regfile + initial_regs = [0] * 32 + initial_regs[3] = 0b101 # predicate mask + initial_regs[9] = 0x90 # source r3 is 0b101 so this will be used + initial_regs[10] = 0x91 # this gets skipped + initial_regs[11] = 0x92 # VL loop runs out before we can use it + # SVSTATE (in this case, VL=3) + svstate = SVP64State() + svstate.vl[0:7] = 3 # VL + svstate.maxvl[0:7] = 3 # MAXVL + print("SVSTATE", bin(svstate.spr.asint())) + # copy before running + expected_regs = deepcopy(initial_regs) + expected_regs[5] = 0x0 # dest ~r3 is 0b010: skip + expected_regs[6] = 0xffff_ffff_ffff_ff90 # 2nd bit of ~r3 is 1 + expected_regs[7] = 0x0 # dest ~r3 is 0b010: skip + + with Program(lst, bigendian=False) as program: + sim = self.run_tst_program(program, initial_regs, svstate) + self._check_regs(sim, expected_regs) + def run_tst_program(self, prog, initial_regs=None, svstate=None, initial_cr=0): -- 2.30.2